RE: [PATCH v3 09/17] scsi: ufs: ufs-exynos: correct timeout value setting registers

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>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@xxxxxxxxxxx]
>Sent: Friday, September 17, 2021 12:24 PM
>To: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>; Avri Altman
><avri.altman@xxxxxxx>; James E . J . Bottomley <jejb@xxxxxxxxxxxxx>; Martin
>K . Petersen <martin.petersen@xxxxxxxxxx>; Krzysztof Kozlowski
><krzysztof.kozlowski@xxxxxxxxxxxxx>
>Cc: Bean Huo <beanhuo@xxxxxxxxxx>; Bart Van Assche
><bvanassche@xxxxxxx>; Adrian Hunter <adrian.hunter@xxxxxxxxx>; Christoph
>Hellwig <hch@xxxxxxxxxxxxx>; Can Guo <cang@xxxxxxxxxxxxxx>; Jaegeuk Kim
><jaegeuk@xxxxxxxxxx>; Gyunghoon Kwon <goodjob.kwon@xxxxxxxxxxx>;
>linux-samsung-soc@xxxxxxxxxxxxxxx; linux-scsi@xxxxxxxxxxxxxxx; Chanho Park
><chanho61.park@xxxxxxxxxxx>; Kiwoong Kim <kwmad.kim@xxxxxxxxxxx>
>Subject: [PATCH v3 09/17] scsi: ufs: ufs-exynos: correct timeout value setting
>registers
>
>PA_PWRMODEUSERDATA0 -> DL_FC0PROTTIMEOUTVAL
>PA_PWRMODEUSERDATA1 -> DL_TC0REPLAYTIMEOUTVAL
>PA_PWRMODEUSERDATA2 -> DL_AFC0REQTIMEOUTVAL
>
>Cc: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
>Cc: Kiwoong Kim <kwmad.kim@xxxxxxxxxxx>
>Cc: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx>
>Signed-off-by: Chanho Park <chanho61.park@xxxxxxxxxxx>
>---
Please add a [Fixes] tag with the original commit which introduce this

With the above fix, feel free to add

Reviewed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>

> drivers/scsi/ufs/ufs-exynos.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c index
>2024e44a09d7..e32f7d09db1a 100644
>--- a/drivers/scsi/ufs/ufs-exynos.c
>+++ b/drivers/scsi/ufs/ufs-exynos.c
>@@ -644,9 +644,9 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba
>*hba,
> 	}
>
> 	/* setting for three timeout values for traffic class #0 */
>-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 8064);
>-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
>28224);
>-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
>20160);
>+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
>+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL),
>28224);
>+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
>
> 	return 0;
> out:
>--
>2.33.0






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