Hi Chanho
> -----Original Message-----
> From: Chanho Park <chanho61.park@xxxxxxxxxxx>
> Sent: 09 July 2021 12:27
> To: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>; James E . J . Bottomley
> <jejb@xxxxxxxxxxxxx>; Martin K . Petersen <martin.petersen@xxxxxxxxxx>
> Cc: Can Guo <cang@xxxxxxxxxxxxxx>; Jaegeuk Kim <jaegeuk@xxxxxxxxxx>;
> Kiwoong Kim <kwmad.kim@xxxxxxxxxxx>; Avri Altman
> <avri.altman@xxxxxxx>; Adrian Hunter <adrian.hunter@xxxxxxxxx>;
> Christoph Hellwig <hch@xxxxxxxxxxxxx>; Bart Van Assche
> <bvanassche@xxxxxxx>; jongmin jeong <jjmin.jeong@xxxxxxxxxxx>;
> Gyunghoon Kwon <goodjob.kwon@xxxxxxxxxxx>; linux-samsung-
> soc@xxxxxxxxxxxxxxx; linux-scsi@xxxxxxxxxxxxxxx; Chanho Park
> <chanho61.park@xxxxxxxxxxx>
> Subject: [PATCH 03/15] scsi: ufs: ufs-exynos: change pclk available max value
>
> To support 167MHz PCLK, we need to adjust the maximum value.
>
> Signed-off-by: Chanho Park <chanho61.park@xxxxxxxxxxx>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
> drivers/scsi/ufs/ufs-exynos.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
> index 67505fe32ebf..475a5adf0f8b 100644
> --- a/drivers/scsi/ufs/ufs-exynos.h
> +++ b/drivers/scsi/ufs/ufs-exynos.h
> @@ -99,7 +99,7 @@ struct exynos_ufs;
> #define PA_HIBERN8TIME_VAL 0x20
>
> #define PCLK_AVAIL_MIN 70000000
> -#define PCLK_AVAIL_MAX 133000000
> +#define PCLK_AVAIL_MAX 167000000
>
> struct exynos_ufs_uic_attr {
> /* TX Attributes */
> --
> 2.32.0
