On 12/22/20 11:11 AM, Kashyap Desai wrote:
Firmware can report various MPI Events.
Support for certain Events (as listed below) are enabled in the driver
and their processing in driver is covered in this patch.
MPI3_EVENT_DEVICE_ADDED
MPI3_EVENT_DEVICE_INFO_CHANGED
MPI3_EVENT_DEVICE_STATUS_CHANGE
MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE
MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST
MPI3_EVENT_SAS_DISCOVERY
MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR
Key support in this patch is device add/removal.
Signed-off-by: Kashyap Desai <kashyap.desai@xxxxxxxxxxxx>
Cc: sathya.prakash@xxxxxxxxxxxx
---
drivers/scsi/mpi3mr/mpi/mpi30_api.h | 2 +
drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h | 2721 ++++++++++++++++++++++++++
drivers/scsi/mpi3mr/mpi/mpi30_sas.h | 46 +
drivers/scsi/mpi3mr/mpi3mr.h | 195 ++
drivers/scsi/mpi3mr/mpi3mr_fw.c | 177 +-
drivers/scsi/mpi3mr/mpi3mr_os.c | 1452 ++++++++++++++
6 files changed, 4592 insertions(+), 1 deletion(-)
create mode 100644 drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
create mode 100644 drivers/scsi/mpi3mr/mpi/mpi30_sas.h
diff --git a/drivers/scsi/mpi3mr/mpi/mpi30_api.h b/drivers/scsi/mpi3mr/mpi/mpi30_api.h
index ca07387536d3..7bdd5aeb23be 100644
--- a/drivers/scsi/mpi3mr/mpi/mpi30_api.h
+++ b/drivers/scsi/mpi3mr/mpi/mpi30_api.h
@@ -14,8 +14,10 @@
#include "mpi30_type.h"
#include "mpi30_transport.h"
+#include "mpi30_cnfg.h"
#include "mpi30_image.h"
#include "mpi30_init.h"
#include "mpi30_ioc.h"
+#include "mpi30_sas.h"
#endif /* MPI30_API_H */
diff --git a/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h b/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
new file mode 100644
index 000000000000..3badb1bb85b1
--- /dev/null
+++ b/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
@@ -0,0 +1,2721 @@
+/*
+ * Copyright 2017-2020 Broadcom Inc. All rights reserved.
+ *
+ * Name: mpi30_cnfg.h
+ * Description: Contains definitions for Configuration messages and pages
+ * Creation Date: 03/15/2017
+ * Version: 03.00.00
+ */
+#ifndef MPI30_CNFG_H
+#define MPI30_CNFG_H 1
+
+/*****************************************************************************
+ * Configuration Page Types *
+ ****************************************************************************/
+#define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00)
+#define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01)
+#define MPI3_CONFIG_PAGETYPE_IOC (0x02)
+#define MPI3_CONFIG_PAGETYPE_UEFI_BSD (0x03)
+#define MPI3_CONFIG_PAGETYPE_SECURITY (0x04)
+#define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11)
+#define MPI3_CONFIG_PAGETYPE_DEVICE (0x12)
+#define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20)
+#define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21)
+#define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23)
+#define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24)
+#define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30)
+#define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31)
+#define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33)
+
+/*****************************************************************************
+ * Configuration Page Attributes *
+ ****************************************************************************/
+#define MPI3_CONFIG_PAGEATTR_MASK (0xF0)
+#define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00)
+#define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10)
+#define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20)
+
+/*****************************************************************************
+ * Configuration Page Actions *
+ ****************************************************************************/
+#define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00)
+#define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01)
+#define MPI3_CONFIG_ACTION_READ_CURRENT (0x02)
+#define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03)
+#define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04)
+#define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05)
+
+/*****************************************************************************
+ * Configuration Page Addressing *
+ ****************************************************************************/
+
+/**** Device PageAddress Format ****/
+#define MPI3_DEVICE_PGAD_FORM_MASK (0xF0000000)
+#define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
+#define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000)
+#define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
+
+/**** SAS Expander PageAddress Format ****/
+#define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
+#define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
+#define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000)
+#define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000)
+#define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
+#define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
+#define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
+
+/**** SAS Phy PageAddress Format ****/
+#define MPI3_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
+#define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
+#define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
+
+/**** SAS Port PageAddress Format ****/
+#define MPI3_SASPORT_PGAD_FORM_MASK (0xF0000000)
+#define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
+#define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
+#define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000FF)
+
+/**** Enclosure PageAddress Format ****/
+#define MPI3_ENCLOS_PGAD_FORM_MASK (0xF0000000)
+#define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
+#define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
+#define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
+
+/**** PCIe Switch PageAddress Format ****/
+#define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000)
+#define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
+#define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000)
+#define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000)
+#define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000)
+#define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16)
+#define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF)
+
+/**** PCIe Link PageAddress Format ****/
+#define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xF0000000)
+#define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000)
+#define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000)
+#define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000FF)
+
+/**** Security PageAddress Format ****/
+#define MPI3_SECURITY_PGAD_FORM_MASK (0xF0000000)
+#define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000)
+#define MPI3_SECURITY_PGAD_FORM_SOT_NUM (0x10000000)
+#define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000FF00)
+#define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000FF)
+
+/*****************************************************************************
+ * Configuration Request Message *
+ ****************************************************************************/
+typedef struct _MPI3_CONFIG_REQUEST {
+ U16 HostTag; /* 0x00 */
+ U8 IOCUseOnly02; /* 0x02 */
+ U8 Function; /* 0x03 */
+ U16 IOCUseOnly04; /* 0x04 */
+ U8 IOCUseOnly06; /* 0x06 */
+ U8 MsgFlags; /* 0x07 */
+ U16 ChangeCount; /* 0x08 */
+ U16 Reserved0A; /* 0x0A */
+ U8 PageVersion; /* 0x0C */
+ U8 PageNumber; /* 0x0D */
+ U8 PageType; /* 0x0E */
+ U8 Action; /* 0x0F */
+ U32 PageAddress; /* 0x10 */
+ U16 PageLength; /* 0x14 */
+ U16 Reserved16; /* 0x16 */
+ U32 Reserved18[2]; /* 0x18 */
+ MPI3_SGE_UNION SGL; /* 0x20 */
+} MPI3_CONFIG_REQUEST, MPI3_POINTER PTR_MPI3_CONFIG_REQUEST,
+ Mpi3ConfigRequest_t, MPI3_POINTER pMpi3ConfigRequest_t;
+
Can you please restrict yourself to _one_ set of codingstyle?
IE please keep your typedefs to all caps, or mixed caps.
But having both is just silly.
Cheers,
Hannes
--
Dr. Hannes Reinecke Kernel Storage Architect
hare@xxxxxxx +49 911 74053 688
SUSE Software Solutions GmbH, Maxfeldstr. 5, 90409 Nürnberg
HRB 36809 (AG Nürnberg), Geschäftsführer: Felix Imendörffer
