On Thu, 05 Nov 2020, Jinpu Wang wrote:
> +cc Viswas
>
> On Mon, Nov 2, 2020 at 11:25 AM Lee Jones <lee.jones@xxxxxxxxxx> wrote:
> >
> > Hasn't been used since 2009.
> >
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/scsi/pm8001/pm8001_hwi.c: In function ‘mpi_set_phys_g3_with_ssc’:
> > drivers/scsi/pm8001/pm8001_hwi.c:415:6: warning: variable ‘value’ set but not used [-Wunused-but-set-variable]
> >
> > Cc: Jack Wang <jinpu.wang@xxxxxxxxxxxxxxx>
> > Signed-off-by: Lee Jones <lee.jones@xxxxxxxxxx>
> > ---
> > drivers/scsi/pm8001/pm8001_hwi.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/scsi/pm8001/pm8001_hwi.c b/drivers/scsi/pm8001/pm8001_hwi.c
> > index 2b7b2954ec31a..cb6959afca7fa 100644
> > --- a/drivers/scsi/pm8001/pm8001_hwi.c
> > +++ b/drivers/scsi/pm8001/pm8001_hwi.c
> > @@ -416,7 +416,7 @@ int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
> > static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
> > u32 SSCbit)
> > {
> > - u32 value, offset, i;
> > + u32 offset, i;
> > unsigned long flags;
> >
> > #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
> > @@ -467,7 +467,6 @@ static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
> > so that the written value will be 0x8090c016.
> > This will ensure only down-spreading SSC is enabled on the SPC.
> > *************************************************************/
> > - value = pm8001_cr32(pm8001_ha, 2, 0xd8);
> AFAIR, the programming manual require first read the register and then
> write, Viswas, can you check?
This is an older patch that I have recently rebased.
For this exact reason, I have no longer take out the read() lines,
only the unused/unchecked variables.
If this is not okay, I will happily re-spin.
> > pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
> >
> > /*set the shifted destination address to 0x0 to avoid error operation */
> >
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
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