Hi Deepak, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on v5.8] [cannot apply to mkp-scsi/for-next scsi/for-next next-20200812] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Deepak-Ukey/pm80xx-Updates-for-the-driver-version-0-1-39/20200812-151808 base: bcf876870b95592b52519ed4aafcf9d95999bc9c config: x86_64-randconfig-c002-20200812 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@xxxxxxxxx> coccinelle warnings: (new ones prefixed by >>) >> drivers/scsi/pm8001/pm8001_init.c:733:3-24: ERROR: reference preceded by free on line 708 vim +733 drivers/scsi/pm8001/pm8001_init.c 624 625 /** 626 * pm8001_init_sas_add - initialize sas address 627 * @chip_info: our ha struct. 628 * 629 * Currently we just set the fixed SAS address to our HBA,for manufacture, 630 * it should read from the EEPROM 631 */ 632 static void pm8001_init_sas_add_and_spinup_config 633 (struct pm8001_hba_info *pm8001_ha) 634 { 635 u8 i, j; 636 u8 sas_add[8]; 637 #ifdef PM8001_READ_VPD 638 /* For new SPC controllers WWN is stored in flash vpd 639 * For SPC/SPCve controllers WWN is stored in EEPROM 640 * For Older SPC WWN is stored in NVMD 641 */ 642 DECLARE_COMPLETION_ONSTACK(completion); 643 struct pm8001_ioctl_payload payload; 644 u16 deviceid; 645 int rc; 646 647 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 648 pm8001_ha->nvmd_completion = &completion; 649 650 if (pm8001_ha->chip_id == chip_8001) { 651 if (deviceid == 0x8081 || deviceid == 0x0042) { 652 payload.minor_function = 4; 653 payload.rd_length = 4096; 654 } else { 655 payload.minor_function = 0; 656 payload.rd_length = 128; 657 } 658 } else if ((pm8001_ha->chip_id == chip_8070 || 659 pm8001_ha->chip_id == chip_8072) && 660 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 661 payload.minor_function = 4; 662 payload.rd_length = 4096; 663 } else { 664 payload.minor_function = 1; 665 payload.rd_length = 4096; 666 } 667 payload.offset = 0; 668 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL); 669 if (!payload.func_specific) { 670 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n")); 671 return; 672 } 673 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 674 if (rc) { 675 kfree(payload.func_specific); 676 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n")); 677 return; 678 } 679 wait_for_completion(&completion); 680 681 for (i = 0, j = 0; i <= 7; i++, j++) { 682 if (pm8001_ha->chip_id == chip_8001) { 683 if (deviceid == 0x8081) 684 pm8001_ha->sas_addr[j] = 685 payload.func_specific[0x704 + i]; 686 else if (deviceid == 0x0042) 687 pm8001_ha->sas_addr[j] = 688 payload.func_specific[0x010 + i]; 689 } else if ((pm8001_ha->chip_id == chip_8070 || 690 pm8001_ha->chip_id == chip_8072) && 691 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 692 pm8001_ha->sas_addr[j] = 693 payload.func_specific[0x010 + i]; 694 } else 695 pm8001_ha->sas_addr[j] = 696 payload.func_specific[0x804 + i]; 697 } 698 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 699 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 700 if (i && ((i % 4) == 0)) 701 sas_add[7] = sas_add[7] + 4; 702 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 703 sas_add, SAS_ADDR_SIZE); 704 PM8001_INIT_DBG(pm8001_ha, 705 pm8001_printk("phy %d sas_addr = %016llx\n", i, 706 pm8001_ha->phy[i].dev_sas_addr)); 707 } > 708 kfree(payload.func_specific); 709 #else 710 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 711 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 712 pm8001_ha->phy[i].dev_sas_addr = 713 cpu_to_be64((u64) 714 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 715 } 716 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 717 SAS_ADDR_SIZE); 718 #endif 719 720 /* For spinning up drives in group */ 721 pm8001_ha->phy_head = -1; 722 pm8001_ha->phy_tail = -1; 723 724 for (i = 0; i < PM8001_MAX_PHYS; i++) 725 pm8001_ha->phy_up[i] = 0xff; 726 727 timer_setup(&pm8001_ha->spinup_timer, 728 (void *)pm8001_spinup_timedout, 0); 729 730 if (pm8001_ha->staggered_spinup == true) { 731 /* spinup interval in unit of 100 ms */ 732 pm8001_ha->spinup_interval = > 733 payload.func_specific[SPINUP_DELAY_OFFSET] * 100; 734 pm8001_ha->spinup_group = 735 payload.func_specific[SPINUP_GROUP_OFFSET]; 736 } else { 737 pm8001_ha->spinup_interval = 0; 738 pm8001_ha->spinup_group = pm8001_ha->chip->n_phy; 739 } 740 741 if (pm8001_ha->spinup_interval > PM80XX_MAX_SPINUP_DELAY) { 742 PM8001_DISC_DBG(pm8001_ha, pm8001_printk( 743 "Spinup delay from Seeprom is %d ms, reset to %d ms\n", 744 pm8001_ha->spinup_interval * 100, PM80XX_MAX_SPINUP_DELAY)); 745 pm8001_ha->spinup_interval = PM80XX_MAX_SPINUP_DELAY; 746 } 747 748 if (pm8001_ha->spinup_group > pm8001_ha->chip->n_phy) { 749 PM8001_DISC_DBG(pm8001_ha, pm8001_printk( 750 "Spinup group from Seeprom is %d, reset to %d\n", 751 pm8001_ha->spinup_group, pm8001_ha->chip->n_phy)); 752 pm8001_ha->spinup_group = pm8001_ha->chip->n_phy; 753 } 754 755 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 756 "Spinup interval : %d Spinup group %d\n", 757 pm8001_ha->spinup_interval, pm8001_ha->spinup_group)); 758 } 759 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
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.config.gz
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