On Fri, Dec 13, 2019 at 2:42 PM Stanley Chu <stanley.chu@xxxxxxxxxxxx> wrote:
>
> Enable clk-gating with customized delayed timer value in
> MediaTek Chipsets.
>
> Signed-off-by: Stanley Chu <stanley.chu@xxxxxxxxxxxx>
Reviewed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
> ---
> drivers/scsi/ufs/ufs-mediatek.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
> index 71e2e0e4ea11..282ad06ec846 100644
> --- a/drivers/scsi/ufs/ufs-mediatek.c
> +++ b/drivers/scsi/ufs/ufs-mediatek.c
> @@ -205,6 +205,9 @@ static int ufs_mtk_init(struct ufs_hba *hba)
> /* Enable runtime autosuspend */
> hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
>
> + /* Enable clock-gating */
> + hba->caps |= UFSHCD_CAP_CLK_GATING;
> +
> /*
> * ufshcd_vops_init() is invoked after
> * ufshcd_setup_clock(true) in ufshcd_hba_init() thus
> @@ -293,6 +296,23 @@ static int ufs_mtk_pre_link(struct ufs_hba *hba)
> return ret;
> }
>
> +static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
> +{
> + unsigned long flags;
> + u32 ah_ms;
> +
> + if (ufshcd_is_clkgating_allowed(hba)) {
> + if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
> + ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
> + hba->ahit);
> + else
> + ah_ms = 10;
> + spin_lock_irqsave(hba->host->host_lock, flags);
> + hba->clk_gating.delay_ms = ah_ms + 5;
> + spin_unlock_irqrestore(hba->host->host_lock, flags);
> + }
> +}
> +
> static int ufs_mtk_post_link(struct ufs_hba *hba)
> {
> /* disable device LCC */
> @@ -308,6 +328,8 @@ static int ufs_mtk_post_link(struct ufs_hba *hba)
> FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3));
> }
>
> + ufs_mtk_setup_clk_gating(hba);
> +
> return 0;
> }
>
> --
> 2.18.0
--
Regards,
Alim
