To expose multiple queues to the upper layer we will need to do some interrupt initialisation earlier - that being to calculate the vectors - so split interrupt_init_v3_hw(). Signed-off-by: John Garry <john.garry@xxxxxxxxxx> --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 497bbf6964f6..29119d0b27a7 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -2409,11 +2409,10 @@ static void setup_reply_map_v3_hw(struct hisi_hba *hisi_hba, int nvecs) /* Don't clean all CQ masks */ } -static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) +static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba) { struct device *dev = hisi_hba->dev; - struct pci_dev *pdev = hisi_hba->pci_dev; - int vectors, rc, i; + int vectors; int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi; if (auto_affine_msi_experimental) { @@ -2445,6 +2444,14 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) } hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW; + return 0; +} + +static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) +{ + struct device *dev = hisi_hba->dev; + struct pci_dev *pdev = hisi_hba->pci_dev; + int rc, i; rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), int_phy_up_down_bcast_v3_hw, 0, @@ -3284,6 +3291,9 @@ hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (hisi_sas_debugfs_enable) hisi_sas_debugfs_init(hisi_hba); + rc = interrupt_preinit_v3_hw(hisi_hba); + if (rc) + goto err_out_ha; rc = scsi_add_host(shost, dev); if (rc) goto err_out_ha; -- 2.17.1