On Thu, Aug 09, 2018 at 01:25:15PM +0000, Janek Kotas wrote:
> This patch adds a DT binding documentation for
> Cadence UFS Host Controller.
>
> Signed-off-by: Jan Kotas <jank@xxxxxxxxxxx>
> ---
> .../devicetree/bindings/ufs/cdns,ufshc.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
>
> diff --git a/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
> new file mode 100644
> index 00000000..a04a4989
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
> @@ -0,0 +1,31 @@
> +* Cadence Universal Flash Storage (UFS) Controller
> +
> +UFS nodes are defined to describe on-chip UFS host controllers.
> +Each UFS controller instance should have its own node.
> +Please see the ufshcd-pltfrm.txt for a list of all available properties.
> +
> +Required properties:
> +- compatible : Compatible list, contains the following controller:
> + "cdns,ufshc"
> + complemented with the JEDEC version:
> + "jedec,ufs-2.0"
> +
> +- reg : Address and length of the UFS register set.
> +- interrupts : One interrupt mapping.
> +- freq-table-hz : Clock frequency table.
> + See the ufshcd-pltfrm.txt for details.
> +- clocks : List of phandle and clock specifier pairs.
> +- clock-names : List of clock input name strings sorted in the same
> + order as the clocks property. "core_clk" is mandatory.
> + Depending on a type of a PHY,
> + the "phy_clk" clock can also be added, if needed.
Unfortunately, you went the wrong direction. The '_clk' part is
redundant. Just 'core' and 'phy'.
With that,
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
> +
> +Example:
> + ufs@fd030000 {
> + compatible = "cdns,ufshc", "jedec,ufs-2.0";
> + reg = <0xfd030000 0x10000>;
> + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
> + freq-table-hz = <0 0>, <0 0>;
> + clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
> + clock-names = "core_clk", "phy_clk";
> + };
> --
> 2.15.0
>
>
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