On Fri, 2018-08-03 at 16:04 +0530, Sreekanth Reddy wrote: > On Fri, Aug 3, 2018 at 3:07 PM, Andy Shevchenko > <andriy.shevchenko@xxxxxxxxxxxxxxx> wrote: > > On Thu, 2018-08-02 at 16:16 -0400, Martin K. Petersen wrote: > > > Andy, > > > > > > Please review the changes Sreekanth made to address your feedback. > > > > From my point of view they look good. > > > > I assume Sreekanth tested them on real hardware and as I remember > > davem@ > > actually the one who possesses sparc machine with this hardware. > > Yes I have tested this patch changes on SPARC64 system and it is > working fine. > Thanks for confirming. >From code prospective Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> > Thanks, > Sreekanth > > > > > > > > > > Swap the I/O memory read value back to cpu endianness before > > > > storing > > > > it > > > > in a data structures which are defined in the MPI headers where > > > > u8 components are not defined in the endianness order. > > > > > > > > In this area from day one mpt3sas driver is using le32_to_cpu() > > > > & > > > > cpu_to_le32() APIs. But in the patch cf6bf9710c > > > > (mpt3sas: Bug fix for big endian systems) we have removed these > > > > APIs > > > > before reading I/O memory which we should haven't done it. So > > > > in this patch I am correcting it by adding these APIs back > > > > before accessing I/O memory. > > > > > > > > v1: Changelog: > > > > Replaced writeq API with __raw_writeq() & mmiowb() APIs. > > > > > > > > > > -- > > Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> > > Intel Finland Oy -- Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> Intel Finland Oy
