On Fri, Jun 29, 2018 at 7:06 PM, James Bottomley <James.Bottomley@xxxxxxxxxxxxxxxxxxxxx> wrote: > On Fri, 2018-06-29 at 10:58 -0400, Chaitra P B wrote: >> "scsi: mpt3sas: Bug fix for big endian systems" >> >> Above patch with commit id "cf6bf9710cabba1fe94a4349f4eb8db623c77ebc" >> was posted to fix sparse warnings. While posting this patch it was >> assumed that readl() & writel() APIs internally calls le32_to_cpu() & >> cpu_to_le32() APIs respectively. Looks like it is not true for all >> architecture > > Just a minute, it damn well should be. The definition of readl/writel > is barriers and little endian (you can see this in asm-generic/io.h). > > Which architecture is getting this wrong? Because it sounds like > that's what we need to fix rather than doing something like this in all > drivers. > > Sparc (and parisc) definitely do the little endian thing, so if this > code is what it takes to get them working again, it looks like you're > double swapping somewhere. I really think cf6bf9710c needs to be > reverted and you should look again at your sparse warnings. Since the > driver is using the non-raw readX/writeX it should be cpu endian > internally which cf6bf9710c upsets. And we definitely won't see the constructions like writeq(cpu_to_le64()) in the code, because it's weird. If I get it correctly it's equivalent to __raw_writeq(). -- With Best Regards, Andy Shevchenko
