On Tue, Oct 17, 2017 at 04:05:40PM +0800, Huacai Chen wrote: > In non-coherent DMA mode, kernel uses cache flushing operations to > maintain I/O coherency, so scsi's block queue should be aligned to > ARCH_DMA_MINALIGN. Otherwise, If a DMA buffer and a kernel structure > share a same cache line, and if the kernel structure has dirty data, > cache_invalidate (no writeback) will cause data corruption. Looks fine to, and I like cleaning up the arcane 0x03 as wel.
