RE: [PATCH] aic94xx: driver assertion in non-x86 BIOS env

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> -----Original Message-----
> From: Matthew Wilcox [mailto:matthew@xxxxxx]
> Sent: Wednesday, March 01, 2006 1:12 PM
> To: Tarte, Robert
> Cc: Jeff Garzik; Mike Anderson; James Bottomley; linux-
> scsi@xxxxxxxxxxxxxxx; Jeff Garzik
> Subject: Re: [PATCH] aic94xx: driver assertion in non-x86 BIOS env
> 
> On Wed, Mar 01, 2006 at 12:57:12PM -0800, Tarte, Robert wrote:
> > I have located an HP machine that is the same flavor as James' (HP
> > Integrity rx2600: ia64 with zx1 chipset).  It exhibits the same
problem.
> > I believe that the architecture may differ with traditional PC/PCI
> > architectures in how it deals with non-aligned PCI access.  When I
> > converted the OCM initialization code to write on qwords instead of
> > dwords, the code was able to pass OCM initialization.  It is
possible
> > that the machine is doing a qword read/modify/write when accessing
OCM
> > memory, which would explain the hang.  I haven't hooked up a PCI
> > analyzer.  The code now gets to the point where it is trying to read
> > NVRAM in order to get the SAS address.  It seems that the machine is
> > unable to retrieve non-aligned byte accesses correctly.  I will
convert
> > the code to pull the correct byte/word/dword from the aligned qword.
> > We'll see if that fixes it.  None of these behaviors are exhibited
on
> > x86, x86_64, powerpc, and ia64 without the zx1 chipset.  I
understand
> > that there may be a few ARM implementations that have similar
issues.
> 
> You're saying that you do an 8-byte non-DMA write to an address
> that's congruent to 4 mod 8?  Based on briefly skimming the internal
> documentation for zx1, I'd say you're invoking undefined behaviour.

Thanks for the confirmation.  Internal documentation for zx1?  Where can
I locate this?  Thanks in advance.

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