On Mon, Jan 16, 2006 at 12:05:17PM +0000, Christoph Hellwig wrote: > > - *maddr = ioremap_nocache(base_page, base_offset + 256); > > + *maddr = ioremap_nocache(base_page, base_offset + 512); > > so how could this work before? In the absence of chip documentation, maybe the registers are mapped several times over, once at +0, once at +256, once at +512, each time with slightly different semantics? We definitely have chips with register files in IO space, Mem space and Config space, so choosing to map the registers several times in the same address space probably just doesn't seem terribly crazy to hardware people ;-) Are Adaptec planning on releasing chip documentation? - : send the line "unsubscribe linux-scsi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
