On 02/16/2018 12:58 PM, Sylwester Nawrocki wrote: > On 02/13/2018 02:40 PM, Andrzej Hajda wrote: >> Declared rates did not match rates generated by PLL. >> As a result driver behaved inconsitently. > > How about changing commit message to something along the lines of: > > "Rates declared in PLL rate tables should match exactly rates calculated > from PLL coefficients. If that is not the case, rate of parent might be being s/parent/PLL's child clock > set not as expected. For instance, if in the PLL rates table we have > a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate > callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate > will return 393216003. If we now attempt to set rate of a PLL's child divider > clock to 393216000/2 its rate will be 131072001, rather than 196608000. > That is the divider will be set to 3 instead of 2, because 393216003/2 is > greater than 196608000. > > To fix this issue declared rates are changed to exactly match rates generated > by a PLL, as calculated from the P, M, S, K coefficients. > > In this patch an erroneous P value for 74176002 output frequency is also > corrected. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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