On Tue, Feb 13, 2018 at 2:40 PM, Andrzej Hajda <a.hajda@xxxxxxxxxxx> wrote:
> Rates declared in PLL rate tables should match exactly rates calculated
> from PLL coefficients. To avoid possible mistakes we can use compile
> time validation.
> The patch introduces such validators and expands all initializers
> with additional input frequency parameter, required to validate rates.
> Since S3C24xx PLLs requires different validators two new macros have
> been introduced to deal with it.
> As the patch adds only compile time validators it should not have impact
> on compiled code.
Cool! One nit below.
(...)
>
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index bbfa57b4e017..492d51691080 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -140,7 +140,7 @@ static const struct samsung_div_clock topc_div_clks[] __initconst = {
> };
>
> static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
> - PLL_36XX_RATE(491519897, 20, 1, 0, 31457),
> + PLL_36XX_RATE(24 * MHZ, 491519897, 20, 1, 0, 31457),
> {},
> };
>
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index 61eb8abbfd9c..b1ee0e801d3e 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -41,35 +41,69 @@ enum samsung_pll_type {
> pll_1460x,
> };
>
> -#define PLL_35XX_RATE(_rate, _m, _p, _s) \
> +/*
> + * To validate PLL rates we need compile time checker.
> + * Since BUILD_BUG_ON does work with initializers, we need some replacement.
I think you meant here:
s/does/does not/
Anyway:
Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
Best regards,
Krzysztof
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