Hi Sylwester,
When I developed the clk-exynos5433.c I referred to the following description.
TRM specified that "Samsung recommends only the values
between 252MH ~ 400MHz in the PMS2460X PMS value" for aud_pll.
It looks like that you refer to clk-exynos5420.c driver.
But, I'm wondering exynos5433 might not guarantee the additional clock
of this patch as the stable clock.
On 2018년 02월 05일 23:22, Sylwester Nawrocki wrote:
> Add more definitions to the exynos5433_aud_pll_rates table so the
> AUD_PLL can be used as a root clock source for the I2S1 and the HDMI
> interface.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@xxxxxxxxxxx>
> ---
> drivers/clk/samsung/clk-exynos5433.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index db270908037a..74b70ddab4d6 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -765,6 +765,14 @@ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initcons
> PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
> PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
> PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
> + PLL_36XX_RATE(200000000U, 200, 3, 3, 0),
> + PLL_36XX_RATE(196608001U, 197, 3, 3, -25690),
> + PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
> + PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
> + PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
> + PLL_36XX_RATE(65536003U, 131, 3, 4, 4719),
> + PLL_36XX_RATE(49152000U, 197, 3, 5, -25690),
> + PLL_36XX_RATE(32768001U, 131, 3, 5, 4719),
> { /* sentinel */ }
> };
>
> --
> 2.14.2
>
>
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
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