[PATCH] drm/exynos: mixer: avoid Oops in vp_video_buffer()

[Tobias Jakobi <tjakobi@xxxxxxxxxxxxxxxxxxxxx>]

If an interlaced video mode is selected, a IOMMU pagefault is
triggered by vp_video_buffer().

Fix the most apparent bugs:
- pitch value for chroma plane
- divide by two of height and vpos

This is more like a band-aid at this point. The VP plane is
still corrupted, but at least there are no more pagefaults.

Signed-off-by: Tobias Jakobi <tjakobi@xxxxxxxxxxxxxxxxxxxxx>
---
 drivers/gpu/drm/exynos/exynos_mixer.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index dc5d79465f9b..c382f99e0f5b 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -485,7 +485,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
 			chroma_addr[1] = chroma_addr[0] + 0x40;
 		} else {
 			luma_addr[1] = luma_addr[0] + fb->pitches[0];
-			chroma_addr[1] = chroma_addr[0] + fb->pitches[0];
+			chroma_addr[1] = chroma_addr[0] + fb->pitches[1];
 		}
 	} else {
 		luma_addr[1] = 0;
@@ -507,25 +507,26 @@ static void vp_video_buffer(struct mixer_context *ctx,
 	vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
 		VP_IMG_VSIZE(fb->height));
 	/* chroma plane for NV12/NV21 is half the height of the luma plane */
-	vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) |
+	vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[1]) |
 		VP_IMG_VSIZE(fb->height / 2));
 
 	vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w);
-	vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
 	vp_reg_write(ctx, VP_SRC_H_POSITION,
 			VP_SRC_H_POSITION_VAL(state->src.x));
-	vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
 
-	vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w);
-	vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x);
 	if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
-		vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2);
-		vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2);
+		vp_reg_write(res, VP_SRC_HEIGHT, state->src.h / 2);
+		vp_reg_write(res, VP_SRC_V_POSITION, state->src.y / 2);
 	} else {
-		vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h);
-		vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y);
+		vp_reg_write(res, VP_SRC_HEIGHT, state->src.h);
+		vp_reg_write(res, VP_SRC_V_POSITION, state->src.y);
 	}
 
+	vp_reg_write(res, VP_DST_WIDTH, state->crtc.w);
+	vp_reg_write(res, VP_DST_H_POSITION, state->crtc.x);
+	vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h);
+	vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y);
+
 	vp_reg_write(ctx, VP_H_RATIO, state->h_ratio);
 	vp_reg_write(ctx, VP_V_RATIO, state->v_ratio);
 
-- 
2.13.5

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