Hi, Kishon Vijay Abraham I <kishon@xxxxxx> writes: > Felipe, > > On Monday 09 October 2017 05:30 PM, Andrzej Pietrasiewicz wrote: >> From: Vivek Gautam <gautam.vivek@xxxxxxxxxxx> >> >> Adding phy calibration sequence for USB 3.0 DRD PHY present on >> Exynos5420/5800 systems. >> This calibration facilitates setting certain PHY parameters viz. >> the Loss-of-Signal (LOS) Detector Threshold Level, as well as >> Tx-Vboost-Level for Super-Speed operations. >> Additionally we also set proper time to wait for RxDetect measurement, >> for desired PHY reference clock, so as to solve issue with enumeration >> of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive >> on the controller. >> >> We are using CR_port for this purpose to send required data >> to override the LOS values. >> >> On testing with USB 3.0 devices on USB 3.0 port present on >> SMDK5420, and peach-pit boards should see following message: >> usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd >> >> and without this patch, should see below shown message: >> usb 1-1: new high-speed USB device number 2 using xhci-hcd >> >> [Also removed unnecessary extra lines in the register macro definitions] >> >> Signed-off-by: Vivek Gautam <gautam.vivek@xxxxxxxxxxx> >> [adapted to use phy_calibrate as entry point] >> Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@xxxxxxxxxxx> >> --- >> drivers/phy/samsung/phy-exynos5-usbdrd.c | 183 +++++++++++++++++++++++++++++++ >> drivers/usb/dwc3/core.c | 7 +- > > are you okay with this patch? if the API is fine for you, I'm okay with it being called from dwc3 core: Acked-by: Felipe Balbi <felipe.balbi@xxxxxxxxxxxxxxx> -- balbi
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