On 01/27/2017 12:05 PM, Sylwester Nawrocki wrote:
> Cc: linux-clk@xxxxxxxxxxxxxxx
>
> On 01/25/2017 09:06 PM, Krzysztof Kozlowski wrote:
>> On Wed, Jan 25, 2017 at 12:51:57PM +0100, Marek Szyprowski wrote:
>>> Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
>>> phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
>>> to setup initial clock configuration for display subsystem in device tree
>>> in order to avoid dependency on the configuration left by the bootloader.
>>>
>>> Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
>>> ---
>>> drivers/clk/samsung/clk-exynos5433.c | 6 ++++--
>>> include/dt-bindings/clock/exynos5433.h | 5 ++++-
>>> 2 files changed, 8 insertions(+), 3 deletions(-)
>>>
>> Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
>>
>> Sylwester,
>> Could you provide a tag with this?
>
> I have the tag prepared already, but please resend the patch to
> linux-clk@xxxxxxxxxxxxxxx and I will reply there.
> The patches were sent only to the linux-samsung-soc mailing list.
Krzysztof, if you need this patch series as a dependency here is the tag:
The following changes since commit 0c744ea4f77d72b3dcebb7a8f2684633ec79be88:
Linux 4.10-rc2 (2017-01-01 14:31:53 -0800)
are available in the git repository at:
git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.11-samsung-dphy
for you to fetch changes up to 698e0d1d22346ef03d7a13fcd9c2cc86a24bf317:
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
(2017-01-27 11:34:00 +0100)
----------------------------------------------------------------
Exporting clocks for MIPI DSI DPHY and the display PLL
frequency list update for Exynos5433 SoC.
----------------------------------------------------------------
Marek Szyprowski (2):
clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
drivers/clk/samsung/clk-exynos5433.c | 8 ++++++--
include/dt-bindings/clock/exynos5433.h | 5 ++++-
2 files changed, 10 insertions(+), 3 deletions(-)
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