Hello, This patchset is a next step to add support for all power domains on Exynos5433 SoCs. This patchset contains patches for initial clocks configuration on TM2/TM2e boards. Till now display subsystem worked only because the clock hierarchy has been configured by the bootloader. However when power domains are added, such configuration might be lost if the display power domain get turned off before display clock controller's probe. Patches have been generated on top of linux-next from 25th January 2017. This is a part of a larger task, which goal is to add support for power domains on Exynos5433 SoCs and TM2/TM2e boards. All patches needed to get it working have been pushed to the following git repo: https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd Best regards Marek Szyprowski Samsung R&D Institute Poland Changelog: v2: - corrected DISP PLL rate from 266MHz to 250MHz (TM2) and 278MHz (TM2e) - added a patch with PLL data for 250MHZ and 278MHz rates v1: - initial version Patch summary: Marek Szyprowski (3): clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 --------- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 29 ++++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 29 ++++++++++++++++++++++ drivers/clk/samsung/clk-exynos5433.c | 8 ++++-- include/dt-bindings/clock/exynos5433.h | 5 +++- 5 files changed, 68 insertions(+), 15 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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