Hi Tobias,
Looks good to me.
Reviewed-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
Best Regards,
Chanwoo Choi
On 2016년 11월 23일 22:51, Tobias Jakobi wrote:
> On the Exynos4412 SoC the DevFreq subsystem adjusts frequency
> of the various internal busses and corresponding voltages.
>
> E.g. the clock of the DMC (dynamic memory controller) bus
> together with the voltage of the MIF regulator are controlled
> by this.
>
> If DMC activity is low and DevFreq has set a lower OPP, the
> following can happen.
>
> If the system is restarted or goes into a suspend/resume-cycle,
> the first-stage (BL0) bootloader takes over, which also
> initializes clocks to default values. Since the PMIC is an
> external component and not part of the SoC, the BL0 doesn't
> set any default voltages. Upon setting the default clocks
> for the DMC bus, the BL0 hangs because the corresponding
> voltage is too low.
>
> To fix this, we make sure to only go into suspend with a 'safe'
> DevFreq configuration.
>
> Signed-off-by: Tobias Jakobi <tjakobi@xxxxxxxxxxxxxxxxxxxxx>
> ---
> drivers/base/power/main.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c
> index 5a94dfa..9cd7e06 100644
> --- a/drivers/base/power/main.c
> +++ b/drivers/base/power/main.c
> @@ -32,6 +32,7 @@
> #include <trace/events/power.h>
> #include <linux/cpufreq.h>
> #include <linux/cpuidle.h>
> +#include <linux/devfreq.h>
> #include <linux/timer.h>
>
> #include "../base.h"
> @@ -943,6 +944,7 @@ void dpm_resume(pm_message_t state)
> dpm_show_time(starttime, state, NULL);
>
> cpufreq_resume();
> + devfreq_resume();
> trace_suspend_resume(TPS("dpm_resume"), state.event, false);
> }
>
> @@ -1582,6 +1584,7 @@ int dpm_suspend(pm_message_t state)
> trace_suspend_resume(TPS("dpm_suspend"), state.event, true);
> might_sleep();
>
> + devfreq_suspend();
> cpufreq_suspend();
>
> mutex_lock(&dpm_list_mtx);
>
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