Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
a board specific item.
Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@xxxxxxxxxxx>
Reviewed-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 23 ++++++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 28 ---------------------------
2 files changed, 23 insertions(+), 28 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index d3fa03fd0230..0f93e795ab2e 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -165,6 +165,29 @@
};
};
+&cmu_fsys {
+ assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
+ <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
+ <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
+ <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
+ <&cmu_top CLK_DIV_SCLK_USBDRD30>,
+ <&cmu_top CLK_DIV_SCLK_USBHOST30>;
+ assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
+ <&cmu_top CLK_MOUT_BUS_PLL_USER>,
+ <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
+ <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
+ <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
+ <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
+ <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
+ <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
+ assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+ <66700000>, <66700000>;
+};
+
&cpu0 {
cpu-supply = <&buck3_reg>;
};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index a80eb4c22c7a..ab2935253cca 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1134,14 +1134,6 @@
clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
<&cmu_fsys CLK_SCLK_USBDRD30>;
clock-names = "usbdrd30", "usbdrd30_susp_clk";
- assigned-clocks =
- <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
- <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
- <&cmu_top CLK_DIV_SCLK_USBDRD30>;
- assigned-clock-parents =
- <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
- <&cmu_top CLK_MOUT_BUS_PLL_USER>;
- assigned-clock-rates = <0>, <0>, <66700000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -1165,12 +1157,6 @@
<&cmu_fsys CLK_SCLK_USBDRD30>;
clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
"itp";
- assigned-clocks =
- <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
- <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>;
- assigned-clock-parents =
- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
- <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
#phy-cells = <1>;
samsung,pmu-syscon = <&pmu_system_controller>;
status = "disabled";
@@ -1185,12 +1171,6 @@
<&cmu_fsys CLK_SCLK_USBHOST30>;
clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
"itp";
- assigned-clocks =
- <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
- <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
- assigned-clock-parents =
- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
- <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
#phy-cells = <1>;
samsung,pmu-syscon = <&pmu_system_controller>;
status = "disabled";
@@ -1201,14 +1181,6 @@
clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
<&cmu_fsys CLK_SCLK_USBHOST30>;
clock-names = "usbdrd30", "usbdrd30_susp_clk";
- assigned-clocks =
- <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
- <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
- <&cmu_top CLK_DIV_SCLK_USBHOST30>;
- assigned-clock-parents =
- <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
- <&cmu_top CLK_MOUT_BUS_PLL_USER>;
- assigned-clock-rates = <0>, <0>, <66700000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
--
1.9.1
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