Hi Krzysztof,
On 2016-11-16 17:54, Krzysztof Kozlowski wrote:
On Wed, Nov 16, 2016 at 02:06:53PM +0100, Marek Szyprowski wrote:
Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
a board specific item.
Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 13 +++++++++++++
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 28 ---------------------------
2 files changed, 13 insertions(+), 28 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 9ea3f32..b7b2482 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -892,6 +892,19 @@
status = "okay";
};
+&cmu_fsys {
If there would be a resubmit, please put it in alphabetical order.
+ assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
+ <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
+ <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
+ <&cmu_top CLK_DIV_SCLK_USBDRD30>;
+ assigned-clock-parents = <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
+ <&cmu_top CLK_MOUT_BUS_PLL_USER>,
+ <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
+ <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
+ assigned-clock-rates = <0>, <0>, <0>, <0>, <66700000>;
I see this is not an equivalent change - some clocks are not assigned
now. I had impression from the commit msg that it will be just a move so
no practical impact. Won't there be a problem with missing clock
assigns?
I've checked those clocks 2 times and I must have been blind. The clock
identifiers are so long that I missed that some PHYCLK related clocks are
for DRD and some for HOST USB. I will add missing assigns in the next
version.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
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