Hi Marek,
2016-11-16 22:06 GMT+09:00 Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>:
> Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
> from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
> a board specific item.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 13 +++++++++++++
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 28 ---------------------------
> 2 files changed, 13 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> index 9ea3f32..b7b2482 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -892,6 +892,19 @@
> status = "okay";
> };
>
> +&cmu_fsys {
> + assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> + <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
> + <&cmu_top CLK_DIV_SCLK_USBDRD30>;
> + assigned-clock-parents = <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> + <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
> + assigned-clock-rates = <0>, <0>, <0>, <0>, <66700000>;
> +};
> +
> &spi_1 {
> cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
> status = "okay";
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index a80eb4c..ab29352 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -1134,14 +1134,6 @@
> clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
> <&cmu_fsys CLK_SCLK_USBDRD30>;
> clock-names = "usbdrd30", "usbdrd30_susp_clk";
> - assigned-clocks =
> - <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> - <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> - <&cmu_top CLK_DIV_SCLK_USBDRD30>;
> - assigned-clock-parents =
> - <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> - <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> - assigned-clock-rates = <0>, <0>, <66700000>;
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
> @@ -1165,12 +1157,6 @@
> <&cmu_fsys CLK_SCLK_USBDRD30>;
> clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
> "itp";
> - assigned-clocks =
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>;
> - assigned-clock-parents =
> - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
> #phy-cells = <1>;
> samsung,pmu-syscon = <&pmu_system_controller>;
> status = "disabled";
> @@ -1185,12 +1171,6 @@
> <&cmu_fsys CLK_SCLK_USBHOST30>;
> clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
> "itp";
> - assigned-clocks =
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
> - assigned-clock-parents =
> - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
> - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
> #phy-cells = <1>;
> samsung,pmu-syscon = <&pmu_system_controller>;
> status = "disabled";
> @@ -1201,14 +1181,6 @@
> clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
> <&cmu_fsys CLK_SCLK_USBHOST30>;
> clock-names = "usbdrd30", "usbdrd30_susp_clk";
> - assigned-clocks =
> - <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
> - <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> - <&cmu_top CLK_DIV_SCLK_USBHOST30>;
> - assigned-clock-parents =
> - <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> - <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> - assigned-clock-rates = <0>, <0>, <66700000>;
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
Looks good to me.
Reviewed-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
--
Best Regards,
Chanwoo Choi
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