On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> Fix CPU operating points for Exynos5800 (it use different
> voltages than Exynos5420 and supports additional frequencies).
> However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
> 1400MHz OPP (for A7 cores) for now as they are not available
> on all boards.
>
> Based on Hardkernel's kernel for ODROID-XU3 board.
>
> Changes by Ben Gamari:
> - Port to operating-points-v2
>
> Cc: Kukjin Kim <kgene.kim@xxxxxxxxxxx>
> Cc: Doug Anderson <dianders@xxxxxxxxxxxx>
> Cc: Javier Martinez Canillas <javier@xxxxxxxxxxxxxxx>
> Cc: Andreas Faerber <afaerber@xxxxxxx>
> Cc: Sachin Kamat <sachin.kamat@xxxxxxxxxx>
> Cc: Thomas Abraham <thomas.ab@xxxxxxxxxxx>
> Signed-off-by: Ben Gamari <ben@xxxxxxxxxxxxxxxx>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@xxxxxxxxxxx>
> ---
> arch/arm/boot/dts/exynos5800.dtsi | 165 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 165 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
> index c0bb356..e417218 100644
> --- a/arch/arm/boot/dts/exynos5800.dtsi
> +++ b/arch/arm/boot/dts/exynos5800.dtsi
> @@ -17,8 +17,173 @@
>
> / {
> compatible = "samsung,exynos5800", "samsung,exynos5";
> +
> + cpu0_opp_table: opp_table0 {
This includes exynos5420.dtsi, so override by label instead of
duplicating full path.
In the same time you don't have to duplicate all data - just override
what you want:
&cpu0_opp_table {
opp00@1800000000 {
opp-microvolt = <1250000>;
};
};
That should be sufficient I think.
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp00@1800000000 {
> + opp-hz = /bits/ 64 <1800000000>;
> + opp-microvolt = <1250000>;
> + clock-latency-ns = <140000>;
> + };
> + opp01@1700000000 {
> + opp-hz = /bits/ 64 <1700000000>;
> + opp-microvolt = <1250000>;
> + clock-latency-ns = <140000>;
> + };
> + opp02@1600000000 {
> + opp-hz = /bits/ 64 <1600000000>;
> + opp-microvolt = <1250000>;
> + clock-latency-ns = <140000>;
> + };
> + opp03@1500000000 {
> + opp-hz = /bits/ 64 <1500000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <140000>;
> + };
> + opp04@1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <140000>;
> + };
> + opp05@1300000000 {
> + opp-hz = /bits/ 64 <1300000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <140000>;
> + };
> + opp06@1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <140000>;
> + };
> + opp07@1100000000 {
> + opp-hz = /bits/ 64 <1100000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <140000>;
> + };
> + opp08@1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <140000>;
> + };
> + opp09@900000000 {
> + opp-hz = /bits/ 64 <900000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <140000>;
> + };
> + opp10@800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt = <900000>;
> + clock-latency-ns = <140000>;
> + };
> + opp11@700000000 {
> + opp-hz = /bits/ 64 <700000000>;
> + opp-microvolt = <900000>;
> + clock-latency-ns = <140000>;
> + };
> + opp12@600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt = <900000>;
> + clock-latency-ns = <140000>;
> + };
> + opp13@500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + opp-microvolt = <900000>;
> + clock-latency-ns = <140000>;
> + };
> + opp14@400000000 {
> + opp-hz = /bits/ 64 <400000000>;
> + opp-microvolt = <900000>;
> + clock-latency-ns = <140000>;
> + };
> + opp15@300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + opp-microvolt = <900000>;
> + clock-latency-ns = <140000>;
> + };
> + opp16@200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-microvolt = <900000>;
> + clock-latency-ns = <140000>;
> + };
> + };
> +
> + cpu1_opp_table: opp_table1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp00@1300000000 {
> + opp-hz = /bits/ 64 <1300000000>;
> + opp-microvolt = <1250000>;
> + clock-latency-ns = <140000>;
> + };
> + opp01@1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1250000>;
> + clock-latency-ns = <140000>;
> + };
> + opp02@1100000000 {
> + opp-hz = /bits/ 64 <1100000000>;
> + opp-microvolt = <1250000>;
> + clock-latency-ns = <140000>;
> + };
> + opp03@1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <140000>;
> + };
> + opp04@900000000 {
> + opp-hz = /bits/ 64 <900000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <140000>;
> + };
> + opp05@800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <140000>;
> + };
> + opp06@700000000 {
> + opp-hz = /bits/ 64 <700000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <140000>;
> + };
> + opp07@600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <140000>;
> + };
> + opp08@500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <140000>;
> + };
> + opp09@400000000 {
> + opp-hz = /bits/ 64 <400000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <140000>;
> + };
> + opp10@300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + opp-microvolt = <900000>;
> + clock-latency-ns = <140000>;
> + };
> + opp11@200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-microvolt = <900000>;
> + clock-latency-ns = <140000>;
> + };
> + };
> };
>
> +&cpu0 { operating-points-v2 = <&cpu0_opp_table>; };
> +&cpu1 { operating-points-v2 = <&cpu0_opp_table>; };
> +&cpu2 { operating-points-v2 = <&cpu0_opp_table>; };
> +&cpu3 { operating-points-v2 = <&cpu0_opp_table>; };
> +
> +&cpu4 { operating-points-v2 = <&cpu1_opp_table>; };
> +&cpu5 { operating-points-v2 = <&cpu1_opp_table>; };
> +&cpu6 { operating-points-v2 = <&cpu1_opp_table>; };
> +&cpu7 { operating-points-v2 = <&cpu1_opp_table>; };
> +
Why? These are set by exynos5420.dtsi already, aren't they?
Best regards,
Krzysztof
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