On 21 January 2015 at 09:50, Chanwoo Choi <cw00.choi@xxxxxxxxxxx> wrote:
> If the clock will be stayed on highest voltage, will reduce
> the considerable benefit of power-consumption.
But this is exactly what you must be doing right now as well..
I think I didn't make it clear enough with an example. Let me
try..
This is how I feel it should look like:
memory_bus_int: memory_bus@1 {
// Regulator is shared for all below
blocks {
peri_block: memory_bus_block1 {
operating-points = <
100000 850000
50000 850000>;
};
display_block: memory_bus_block2 {
operating-points = <
200000 950000
160000 950000
100000 925000
80000 850000
50000 850000>;
};
isp_block: memory_bus_block3 {
operating-points = <
200000 950000
100000 925000
80000 850000
50000 850000>;
};
gps_block: memory_bus_block4 {
operating-points = <
300000 950000
200000 950000
133000 925000
100000 850000
50000 850000>;
};
Now suppose these are the requirements from all the blocks
at any point of time:
- block1: 100000 850000
- block2: 100000 925000
- block3: 80000 850000
- block4: 133000 925000
Now, all of them can control freq separately and we don't need to
worry for that. But regulator is shared between them. We can check
what's the highest voltage requested at this point of time and can
switch to that.
i.e. 925000 in this case. And that's not the highest possible one.
And you will reach to similar conclusion with your current code as
well I believe.
> I think it is DFS instead of DVFS. Is it right?
No. I am still talking about DVFS, V being the highest requested one.
> What is the correct picture? do you need more detailed explanation
> of Exynos memory bus structure?
The correct picture is what i showed in the above dts example.
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