>
> This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has
> one memory bus to translate data between DRAM and eMMC/sub-IPs because
> Exynos4210 must need only one regulator for memory bus.
>
> Following list specifies the detailed relation between memory bus clock and
> sub-IPs:
> - DMC/ACP clock : DMC (Dynamic Memory Controller)
> - ACLK200 clock : LCD0
> - ACLK100 clock : PERIL/PERIR/MFC(PCLK)
> - ACLK160 clock : CAM/TV/LCD0/LCD1
> - ACLK133 clock : FSYS/GPS
> - GDL/GDR clock : leftbus/rightbus
> - SCLK_MFC clock : MFC
>
> Cc: Kukjin Kim <kgene@xxxxxxxxxx>
> Cc: Myungjoo Ham <myungjoo.ham@xxxxxxxxxxx>
> Cc: Kyungmin Park <kyungmin.park@xxxxxxxxxxx>
> Signed-off-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
Acked-by: MyungJoo Ham <myungjoo.ham@xxxxxxxxxxx>
Revisiting good old days..?
(good to see the first busfreq driver experimented with is
being DT-nized... :) )
Cheers,
MyungJoo
��.n��������+%������w��{.n�����{��Ʀ����)�� jg��� �����ݢj����G���� ���j:+v���w�m������w�������h�����٥
