This patch adds System MMU nodes that are specific to Exynos4210/4x12 series.
Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
---
arch/arm/boot/dts/exynos4.dtsi | 118 ++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos4210.dtsi | 23 ++++++++
arch/arm/boot/dts/exynos4x12.dtsi | 82 ++++++++++++++++++++++++++
3 files changed, 223 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index a59b3fae3680..ca219ed0378c 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -183,6 +183,7 @@
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
samsung,sysreg = <&sys_reg>;
+ iommus = <&sysmmu_fimc0>;
status = "disabled";
};
@@ -194,6 +195,7 @@
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
samsung,sysreg = <&sys_reg>;
+ iommus = <&sysmmu_fimc1>;
status = "disabled";
};
@@ -205,6 +207,7 @@
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
samsung,sysreg = <&sys_reg>;
+ iommus = <&sysmmu_fimc2>;
status = "disabled";
};
@@ -216,6 +219,7 @@
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
samsung,sysreg = <&sys_reg>;
+ iommus = <&sysmmu_fimc3>;
status = "disabled";
};
@@ -404,6 +408,8 @@
clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
clock-names = "mfc", "sclk_mfc";
status = "disabled";
+ iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
+ iommu-names = "left", "right";
};
serial_0: serial@13800000 {
@@ -669,6 +675,7 @@
power-domains = <&pd_lcd0>;
samsung,sysreg = <&sys_reg>;
status = "disabled";
+ iommus = <&sysmmu_fimd0>;
};
hdmi: hdmi@12D00000 {
@@ -691,6 +698,117 @@
interrupts = <0 91 0>;
reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
power-domains = <&pd_tv>;
+ iommus = <&sysmmu_tv>;
status = "disabled";
};
+
+ sysmmu_mfc_l: sysmmu@13620000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x13620000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <5 5>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
+ power-domains = <&pd_mfc>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_mfc_r: sysmmu@13630000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x13630000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <5 6>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
+ power-domains = <&pd_mfc>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_tv: sysmmu@12E20000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12E20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <5 4>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
+ power-domains = <&pd_tv>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimc0: sysmmu@11A20000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11A20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
+ power-domains = <&pd_cam>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimc1: sysmmu@11A30000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11A30000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 3>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
+ power-domains = <&pd_cam>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimc2: sysmmu@11A40000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11A40000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 4>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
+ power-domains = <&pd_cam>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimc3: sysmmu@11A50000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11A50000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 5>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
+ power-domains = <&pd_cam>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_jpeg: sysmmu@11A60000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11A60000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 6>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
+ power-domains = <&pd_cam>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_rotator: sysmmu@12A30000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12A30000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <5 0>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
+ power-domains = <&pd_lcd0>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimd0: sysmmu@11E20000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x11E20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <5 2>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
+ power-domains = <&pd_lcd0>;
+ #iommu-cells = <0>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index fc17cdfa90e6..a2acb8b93785 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -160,6 +160,7 @@
interrupts = <0 89 0>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
+ iommus = <&sysmmu_g2d>;
status = "disabled";
};
@@ -201,4 +202,26 @@
<&clock CLK_VP>, <&clock CLK_MOUT_MIXER>,
<&clock CLK_SCLK_MIXER>;
};
+
+ sysmmu_g2d: sysmmu@12A20000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12A20000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 7>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+ power-domains = <&pd_lcd0>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimd1: sysmmu@12220000 {
+ compatible = "samsung,exynos-sysmmu";
+ interrupt-parent = <&combiner>;
+ reg = <0x12220000 0x1000>;
+ interrupts = <5 3>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
+ power-domains = <&pd_lcd1>;
+ #iommu-cells = <0>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e577bd0106b6..d175eb34de7b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -150,6 +150,7 @@
interrupts = <0 89 0>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
+ iommus = <&sysmmu_g2d>;
status = "disabled";
};
@@ -199,6 +200,7 @@
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE0>;
clock-names = "flite";
+ iommus = <&sysmmu_fimc_lite0>;
status = "disabled";
};
@@ -209,6 +211,7 @@
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE1>;
clock-names = "flite";
+ iommus = <&sysmmu_fimc_lite1>;
status = "disabled";
};
@@ -237,6 +240,9 @@
"mcuispdiv1", "uart", "aclk200",
"div_aclk200", "aclk400mcuisp",
"div_aclk400mcuisp";
+ iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
+ <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
+ iommu-names = "isp", "drc", "fd", "mcuctl";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -294,4 +300,80 @@
clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_VP>;
};
+
+ sysmmu_g2d: sysmmu@10A40000{
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x10A40000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <4 7>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimc_isp: sysmmu@12260000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12260000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 2>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu";
+ clocks = <&clock CLK_SMMU_ISP>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimc_drc: sysmmu@12270000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12270000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 3>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu";
+ clocks = <&clock CLK_SMMU_DRC>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimc_fd: sysmmu@122A0000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x122A0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 4>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu";
+ clocks = <&clock CLK_SMMU_FD>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimc_mcuctl: sysmmu@122B0000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x122B0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 5>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu";
+ clocks = <&clock CLK_SMMU_ISPCX>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimc_lite0: sysmmu@123B0000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x123B0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 0>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_fimc_lite1: sysmmu@123C0000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x123C0000 0x1000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 1>;
+ power-domains = <&pd_isp>;
+ clock-names = "sysmmu", "master";
+ clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
+ #iommu-cells = <0>;
+ };
};
--
1.9.2
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