This patch adds the documentation for generic exynos memory bus frequency
driver.
Cc: MyungJoo Ham <myungjoo.ham@xxxxxxxxxxx>
Cc: Kyungmin Park <kyungmin.park@xxxxxxxxxxx>
Cc: Kukjin Kim <kgene@xxxxxxxxxx>
Signed-off-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
Acked-by: MyungJoo Ham <myungjoo.ham@xxxxxxxxxxx>
---
.../devicetree/bindings/devfreq/exynos-bus.txt | 188 +++++++++++++++++++++
1 file changed, 188 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
new file mode 100644
index 0000000..6323dcf
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -0,0 +1,188 @@
+
+* Generic Exynos Memory Bus device
+
+The Samsung Exynos SoCs have many memory buses for data transfer between DRAM
+memory and MMC/sub-IP in SoC. Almost Exynos SoCs have the common architecture
+for memory buses. Generally, Exynos SoC express the memory bus by using memory
+bus group and block. The memory bus group has one more memory bus blocks and
+OPP table (including frequency and voltage for DVFS), regulator, devfreq-event
+devices. Each memory bus block has a clock for own memory bus speen and
+frequency table for DVFS. There are a little different among Exynos SoCs
+because each Exynos SoC has the different sub-IP and differnt memory bus.
+So, this difference should be specified in devicetree file.
+
+Required properties for memory bus group:
+- compatible: Should be "samsung,exynos-memory-bus".
+- operating-points: the OPP table including frequency/voltage information to
+ support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+- devfreq-events: the devfreq-event device to monitor the curret state of
+ memory bus group.
+- vdd-mem-supply: the regulator to provide memory bus group with the voltage.
+
+Optional properties for memory bus group:
+- exynos,saturation-ratio: the percentage value which is used to calibrate
+ the memory performance count againt memory cycle count.
+
+Required properties for memory bus block:
+- clock-names : the name of clock used by the memory bus, "memory-bus".
+- clocks : phandles for clock specified in "clock-names" property.
+- #clock-cells: should be 1.
+- frequency: the frequency table to support DVFS feature.
+
+Example1 : Memory bus group/block in exynos3250.dtsi are listed below.
+ Exynos3250 has two memory bus group (MIF, INT group). MIF (Memory
+ Interface) memory bus group includes one memory bus block between
+ DRAM and eMMC. Also, INT (Internal) memory bus group includes eight
+ memory bus blocks which support each sub-IP between DRAM and sub-IP.
+
+ memory_bus_mif: memory_bus@0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 875000
+ 200000 800000
+ 133000 800000
+ 100000 800000
+ 50000 800000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 133000
+ 100000
+ 50000>;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus@1 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 950000
+ 200000 950000
+ 133000 925000
+ 100000 850000
+ 80000 850000
+ 50000 850000>;
+
+ status = "disabled";
+
+ blocks {
+ peri_block: memory_bus_block1 {
+ clocks = <&cmu CLK_DIV_ACLK_100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ display_block: memory_bus_block2 {
+ clocks = <&cmu CLK_DIV_ACLK_160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000
+ 80000
+ 80000
+ 50000>;
+ };
+
+ isp_block: memory_bus_block3 {
+ clocks = <&cmu CLK_DIV_ACLK_200>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 100000
+ 80000
+ 50000
+ 50000>;
+ };
+
+ gps_block: memory_bus_block4 {
+ clocks = <&cmu CLK_DIV_ACLK_266>;
+ clock-names = "memory-bus";
+ frequency = <
+ 300000
+ 200000
+ 133000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ mcuisp_block: memory_bus_block5 {
+ clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 50000
+ 50000
+ 50000
+ 50000>;
+ };
+
+ leftbus_block: memory_bus_block6 {
+ clocks = <&cmu CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block7 {
+ clocks = <&cmu CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block8 {
+ clocks = <&cmu CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 200000
+ 133000
+ 100000
+ 80000>;
+ };
+ };
+ };
+
+Example2 : Usage case to handle the frequency/voltage of memory bus on runtime
+ in exynos3250-rinato.dts are listed below.
+
+ &memory_bus_mif {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-mem-supply = <&buck1_reg>;
+ status = "okay";
+ };
+
+ &memory_bus_int {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-mem-supply = <&buck3_reg>;
+ status = "okay";
+ };
--
1.8.5.5
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