Hi Tomasz, On Tue, Oct 14, 2014 at 6:56 AM, Anton Tikhomirov <av.tikhomirov@xxxxxxxxxxx> wrote: > Hello, > >> Hi Anton, >> >> On 13.10.2014 06:54, Anton Tikhomirov wrote: >> > Hi Vivek, >> > >> >> Exynos7 also has a separate special gate clock going to the IP >> >> apart from the usual AHB clock. So add support for the same. >> > >> > As we discussed before, Exynos7 SoCs have 7 clocks to be controlled >> > by the driver. Adding only sclk is not enough. >> > >> >> I'm quite interested in this discussion. Has it happened on mailing >> lists? > > No, we used company messenger for the discussion. Yea, we head a round of discussion at our end regarding this, and we are going to get more clarity on this from our H/W team too, this week. > >> >> In general, previous SoCs also gave the possibility of controlling all >> the bus clocks separately, in addition to bulk gates, but there was no > > correct > >> real advantage in using those, while burdening the clock tree with >> numerous clocks. Isn't Exynos7 similar in this aspect? > > Exynos7 doesn't have "Gating all clocks for USBDRD30" bit. The clocks > should be controlled separately. true, on Exynos7 we have separate gates for the available clocks going to USB-DRD block. So we will have to add these basic required number of clocks. -- Best Regards Vivek Gautam Samsung R&D Institute, Bangalore India -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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