On 14.07.2014 15:38, Thomas Abraham wrote: > From: Thomas Abraham <thomas.ab@xxxxxxxxxxx> > > Register the PLL configuration data for APLL and KPLL on Exynos5420. This > configuration data table specifies PLL coefficients for supported PLL > clock speeds when a 24MHz clock is supplied as the input clock source > for these PLLs. > > Cc: Tomasz Figa <t.figa@xxxxxxxxxxx> > Signed-off-by: Thomas Abraham <thomas.ab@xxxxxxxxxxx> > Reviewed-by: Amit Daniel Kachhap <amit.daniel@xxxxxxxxxxx> > Tested-by: Arjun K.V <arjun.kv@xxxxxxxxxxx> > --- > drivers/clk/samsung/clk-exynos5420.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > Looks good. Will apply. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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