On 2014년 06월 23일 14:32, Rahul Sharma wrote:
> Allowing only one layer update per vsync can cause issues
> while there are update available for both layers. There is
> a good amount of possibility to loose updates if we allow
> single update per vsync.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@xxxxxxxxxxx>
> ---
> drivers/gpu/drm/exynos/exynos_mixer.c | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
> index d359501..6773b03 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -511,13 +511,8 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
> static void mixer_layer_update(struct mixer_context *ctx)
> {
> struct mixer_resources *res = &ctx->mixer_res;
> - u32 val;
> -
> - val = mixer_reg_read(res, MXR_CFG);
>
> - /* allow one update per vsync only */
> - if (!(val & MXR_CFG_LAYER_UPDATE_COUNT_MASK))
> - mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
> + mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
Rahul, it looks good to me and ok as is. But above codes don't consider
Exynos4 series. In case of Exynos4xxx SoC,
MXR_CFG_LAYER_UPDATE_COUNT_MASK and MXR_CFG_LAYER_UPDATE of MIXER_CFG
register are reserved fields. So can you work that patch to be
considered for Exynos4xxx SoC? That patch would be additional one.
Anyway, will apply it as is, and I will wait for the additional patch.
Thanks,
Inki Dae
> }
>
> static void mixer_graph_buffer(struct mixer_context *ctx, int win)
>
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