On Friday 03 of January 2014 14:37:10 Arnd Bergmann wrote: > On Friday 03 January 2014, Tushar Behera wrote: > > Hi, > > > > We are getting boot-time system hang on Exynos4210-based Origen board > > if the kernel (right now testing v3.13-rc6) is built using > > exynos_defconfig, disabling SMP support and enabling CPU_IDLE support. > > The boot log can be found here[1]. > > > > Git bisect points to following commit. > > > > commit 87107d89052bcec1fe91b309631de4ed294a5171 > > Author: Arnd Bergmann <arnd@xxxxxxxx> > > Date: Wed Jun 19 01:36:52 2013 +0900 > > > > ARM: EXYNOS: Remove legacy L2X0 initialization > > > > Since Exynos is now supporting only DT-based boot, the old L2X0 > > initialization code is not needed anymore, so exynos4_l2x0_cache_init() > > can be greatly simplified. > > > > Signed-off-by: Arnd Bergmann <arnd@xxxxxxxx> > > Signed-off-by: Tomasz Figa <t.figa@xxxxxxxxxxx> > > Signed-off-by: Kyungmin Park <kyungmin.park@xxxxxxxxxxx> > > Signed-off-by: Kukjin Kim <kgene.kim@xxxxxxxxxxx> > > > > Reverting the changes, the kernel boots up. > > > > Any idea what else we might be missing? > > > > [1] http://pastebin.com/0mP6ML4y > > Hmm, the boot log contains no message about the l2 cache controller getting > initialized, which means that l2x0_of_init probably failed before calling > l2x0_init. It also seems that the dts files distributed with the kernel > are lacking nodes for the l2x0 device, which is indeed a perfectly good > explanation although it doesn't explain at all why it ever worked on > any system with my patch. > > Can you check if there is a correct cache controller node in your device > tree, and whether it works when you add one? If so, we should probably > add a couple of stable backport patches to the dts files. It would also > be a good time to get rid of the L2_AUX_VAL and L2_AUX_MASK defines and > just read the respective settings from DT. Tushar, do you maybe also have CONFIG_CACHE_L2X0 enabled? Generally I can see two different issues here: 1) Broken handling of L2 cache in plat-samsung/sleep.S. It assumes that whenever CONFIG_CACHE_L2X0 is enabled, L2 cache is enabled too. This needs to go away. On normal resume from sleep, there is no need to do anything with L2X0 at such early stage. This reinitialization can be safely done later, by calling generic outer_resume(). The problem shows up when you look at AFTR and LPA idle modes. They keep L2 cache contents, but L2X0 registers must be restored to let the cache operate normally. This must happen early enough to keep cache data consistent. Still, the code doing this must consider whether the cache was enabled before entering AFTR/LPA and whether secure firmware is used (see below), so this is a bit tricky. 2) There is no L2 cache controller node in Exynos4*.dtsi. It should be added, but L2 cache can't be enabled on all boards yet, since on boards where secure firmware is enabled, special configuration involving SMC calls is required. Patches for this are queued on my work queue, but it's quite tricky due to 1), which needs to consider whether secure firmware is enabled or not. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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