This is a clean-up series for the Exynos 5250 clock driver. It consists mostly of stylistical fixes and also changes making the clock tree defined by the driver represent more closely the real clock tree of the SoC. On Exynos 5250 based Arndale board: Tested-by: Tomasz Figa <t.figa@xxxxxxxxxxx> Tomasz Figa (7): clk: samsung: exynos5250: Sort definitions by registers and bitfield clk: samsung: exynos5250: Make names of mux and div clocks consistent clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domain clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain clk: samsung: exynos5250: Add missing unpopulated mux parents clk: samsung: exynos5250: Correct parent list of audio muxes clk: samsung: exynos5250: Fix parents of gate clocks from MFC domain drivers/clk/samsung/clk-exynos5250.c | 404 ++++++++++++++++++++++------------- 1 file changed, 256 insertions(+), 148 deletions(-) -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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