Hi Tomasz, >> On Wed, Sep 25, 2013 at 4:52 PM, Lukasz Majewski <l.majewski@xxxxxxxxxxx> wrote: >> > In the exynos4x12_set_apll() function, the APLL frequency is set with >> > direct register manipulation. >> > >> > Such approach is not allowed in the common clock framework. The frequency >> > is changed, but the corresponding clock value is not updated. This causes >> > wrong frequency read from cpufreq's cpuinfo_cur_freq sysfs attribute. >> > >> >> This patch looks incomplete, leaving the driver in untidy state, perhaps its >> doesn't fix the above stated problem completely. what about >> if (!exynos4x12_pms_change(old_index, new_index)) becomes true? >> >> IMHO, this driver needs lot more work in addition to this patch to cleanly and >> completely move the cpufreq driver to common clock framework. > > I agree that the other case needs to be handled as well. Basically the > whole conditional block dependent on exynos4x12_pms_change() can be safely > dropped, because this condition is already handled in PLL driver. > Exactly! > Lukasz is already working on further rework of this driver to clean it up > from legacy code, but this will have to wait for 3.13, as 3.12 is already > in rc stage and only fixes can be accepted for it. > >> For fixing this issue urgently, setting CLK_GET_RATE_NOCACHE for apll >> in clk driver can also be quicker fix. > > Unfortunately this is not how this flag works. It only makes > clk_get_rate() call ->recalc_rate() operation of the clock instead of > instantly returning cached rate - it doesn't seem to work recursively. > hmm.. yes it can't help in our case as it recursively walks only the subtree of clk but in our case we are changing rate of parent. Regards, Yadwinder -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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