On Fri, Aug 23, 2013 at 02:05:39PM +0530, Pratyush Anand wrote:
> On Fri, Aug 23, 2013 at 02:04:20PM +0800, Jingoo Han wrote:
[...]
> > +
> > static struct hw_pci dw_pci;
> >
> > unsigned long global_io_offset;
> > @@ -144,6 +152,205 @@ int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
> > return ret;
> > }
> >
>
> [...]
>
> > int dw_pcie_link_up(struct pcie_port *pp)
> > {
> > if (pp->ops->link_up)
> > @@ -225,6 +432,13 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> > return -EINVAL;
> > }
> >
> > + if (IS_ENABLED(CONFIG_PCI_MSI)) {
> > + if (of_property_read_u32(np, "msi-base", &pp->msi_irq_start)) {
> > + dev_err(pp->dev, "Failed to parse the number of lanes\n");
> > + return -EINVAL;
> > + }
> > + }
> > +
>
> What if an implementor want to use irq_domain method for msi_irq_start
> allocation? Is it fine to return error if msi-base is not passed from
> dt?
I agree. This should be using an IRQ domain to represent the MSI
controller. Both Tegra and Marvell drivers do that already and if Exynos
can follow that same path it will increase the chances of refactoring
common bits.
Also the error message doesn't quite match up with what the code is
doing. =)
Thierry
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