Hi Jingoo,
On 12 August 2013 14:26, Jingoo Han <jg1.han@xxxxxxxxxxx> wrote:
> This patch adds support for Message Signaled Interrupt in the
> Exynops PCIe diver using Synopsys designware PCIe core IP.
s/Exynops PCIe diver/Exynos PCIe driver
>
> Signed-off-by: Siva Reddy Kallam <siva.kallam@xxxxxxxxxxx>
> Signed-off-by: Srikanth T Shivanand <ts.srikanth@xxxxxxxxxxx>
> Signed-off-by: Jingoo Han <jg1.han@xxxxxxxxxxx>
> Cc: Pratyush Anand <pratyush.anand@xxxxxx>
> Cc: Mohit KUMAR <Mohit.KUMAR@xxxxxx>
> ---
> arch/arm/boot/dts/exynos5440.dtsi | 2 +
> arch/arm/mach-exynos/Kconfig | 1 +
> drivers/pci/host/pci-exynos.c | 60 ++++++++++
> drivers/pci/host/pcie-designware.c | 213 ++++++++++++++++++++++++++++++++++++
> drivers/pci/host/pcie-designware.h | 8 ++
> 5 files changed, 284 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
> index 586134e..3746835 100644
> --- a/arch/arm/boot/dts/exynos5440.dtsi
> +++ b/arch/arm/boot/dts/exynos5440.dtsi
> @@ -249,6 +249,7 @@
> interrupt-map-mask = <0 0 0 0>;
> interrupt-map = <0x0 0 &gic 53>;
> num-lanes = <4>;
> + msi-base = <200>;
Please update the bindings documentation too.
> };
>
> pcie@2a0000 {
> @@ -269,5 +270,6 @@
[snip]
>
> +#ifdef CONFIG_PCI_MSI
> +static void exynos_pcie_clear_irq_level(struct pcie_port *pp)
> +{
> + u32 val;
> + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + void __iomem *elbi_base = exynos_pcie->elbi_base;
> +
> + val = readl(elbi_base + PCIE_IRQ_LEVEL);
> + writel(val, elbi_base + PCIE_IRQ_LEVEL);
Sorry, I did not get this. Writing the value read from the same
register without any operation.
--
With warm regards,
Sachin
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