On Friday 07 June 2013 18:19:40 Jingoo Han wrote: > Hi Jason Gunthorpe, > > I implemented 'Single domain' with Exynos PCIe for last two months; > however, it cannot work properly due to the hardware restriction. > Each MEM region is hard-wired. > > Thus, I will send Exynos PCIe V3 patch as 'Separate domains'. Yes, I think that is best, if the hardware is clearly designed as separate domains, this is what we should do by default in the driver. For the Marvell case with its 10 separate ports, much more address space would be wasted by having one domain per port and that hardware let us work around it by remapping the physical address space windows. For Exynos there is much less to lose and I too cannot see how it would be done in the first place. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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