> > + /* CLK_DIV max is 256 */ > > + for (i = 0; i < 256; i++) { > > + utemp1 = utemp0 / (i + 1); > > + /* SCLK_L/H max is 256 / 2 */ > > + if (utemp1 < 128) { > I think TSCLK_L and TSCLK_H both can be configured upto 255.Why > limiting it to < 128 ? > By limiting it to < 128 dont we achieve lesser SCL clock? Thanks for reviewing but please quote only the relevant part of the message (like I did). This improves readability a lot. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html