On 28 December 2012 17:10, Naveen Krishna Chatradhi
<ch.naveen@xxxxxxxxxxx> wrote:
> Adds clock gating bits for High Speed I2C channels 0, 1, 2 and 3.
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@xxxxxxxxxxx>
> ---
> arch/arm/mach-exynos/clock-exynos5.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
> index 0208c3a..f9fa0c7 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -753,6 +753,30 @@ static struct clk exynos5_init_clocks_off[] = {
> .enable = exynos5_clk_ip_peric_ctrl,
> .ctrlbit = (1 << 27),
> }, {
> + .name = "hsi2c",
> + .devname = "exynos5-hsi2c.0",
> + .enable = exynos5_clk_ip_peric_ctrl,
> + .parent = &exynos5_clk_aclk_66.clk,
> + .ctrlbit = (1 << 28),
> + }, {
> + .name = "hsi2c",
> + .devname = "exynos5-hsi2c.1",
> + .enable = exynos5_clk_ip_peric_ctrl,
> + .parent = &exynos5_clk_aclk_66.clk,
> + .ctrlbit = (1 << 29),
> + }, {
> + .name = "hsi2c",
> + .devname = "exynos5-hsi2c.2",
> + .enable = exynos5_clk_ip_peric_ctrl,
> + .parent = &exynos5_clk_aclk_66.clk,
> + .ctrlbit = (1 << 30),
> + }, {
> + .name = "hsi2c",
> + .devname = "exynos5-hsi2c.3",
> + .enable = exynos5_clk_ip_peric_ctrl,
> + .parent = &exynos5_clk_aclk_66.clk,
> + .ctrlbit = (1 << 31),
> + }, {
> .name = "usbhost",
> .enable = exynos5_clk_ip_fsys_ctrl ,
> .ctrlbit = (1 << 18),
> --
> 1.7.9.5
Any comments on this patch please.
>
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--
Shine bright,
(: Nav :)
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