The control bits for mfc_l and mfc_r sysmmus are incorrectly set.
This patch interchanges the control bits so that the mfc sysmmus
function correctly.
Signed-off-by: Prathyush K <prathyush.k@xxxxxxxxxxx>
---
arch/arm/mach-exynos/clock-exynos5.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 0208c3a..730d54c 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -873,13 +873,13 @@ static struct clk exynos5_init_clocks_off[] = {
.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.enable = &exynos5_clk_ip_mfc_ctrl,
.ops = &exynos5_gate_clk_ops,
- .ctrlbit = (1 << 1),
+ .ctrlbit = (1 << 2),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
.enable = &exynos5_clk_ip_mfc_ctrl,
.ops = &exynos5_gate_clk_ops,
- .ctrlbit = (1 << 2),
+ .ctrlbit = (1 << 1),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
--
1.8.0
--
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