Hi Prasanna, On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote: > This patch adds a software workaround to the hardware > problem found in exynos5 while powergating. > > It is observed that CLK_TOP_SRC3 register gets modified if > the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets > set to XXTI which results in the device running very slow . > A big drop in performance is noticed whilerunning the video. > This issue also occurs while powergating MFC. > > The value of clock source register is restored once the powergating > operation is completed. Is the problem really related to power gating at all? From what you described in comment in the code, it seems like it's a problem with suspend/resume, not power gating, so it should be rather saved on suspend and restored on resume. Please recheck clock save/restore part of power management code. Altering clock configuration registers from power domain code looks really ugly... Best regards, Tomasz Figa -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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