CC: Doug Anderson.
On Wed, Dec 19, 2012 at 5:02 AM, Sylwester Nawrocki
<sylvester.nawrocki@xxxxxxxxx> wrote:
> On 12/18/2012 04:39 PM, Vivek Gautam wrote:
>>
>> Adding base address information required for enabling
>> USB 3.0 DRD phy on exynos5250 SOC.
>>
>> Signed-off-by: Vivek Gautam<gautam.vivek@xxxxxxxxxxx>
>> ---
>> arch/arm/boot/dts/exynos5250.dtsi | 3 ++-
>> 1 files changed, 2 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
>> b/arch/arm/boot/dts/exynos5250.dtsi
>> index bbdb2c2..07b7477 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -316,7 +316,8 @@
>>
>> usbphy@12130000 {
>> compatible = "samsung,exynos5250-usbphy";
>> - reg =<0x12130000 0x100>;
>> + reg =<0x12130000 0x100>,
>> + <0x12100000 0x100>;
>
>
> Doesn't this second memory region mean distinct PHY controller device ?
> Why separate usbphy node can't/shouldn't be created for it ?
>
>> samsung,usb-phyhandle =<&phy_h0&phy_h1&phy_h2>;
>> samsung,enable-mask =<1>;
>> };
>
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--
Thanks & Regards
Vivek
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