On Fri, Sep 14, 2012 at 9:57 AM, Jingoo Han <jg1.han@xxxxxxxxxxx> wrote:
>
> On Wednesday, September 12, 2012 8:49 PM Leela Krishna Amudala wrote
> >
> > This patch adds the bus clock for FIMD and changes the device name for
> > lcd clock
> > also sets mout_mpll_user as parent clock to fimd
> >
> > Signed-off-by: Leela Krishna Amudala <l.krishna@xxxxxxxxxxx>
> > ---
> > arch/arm/mach-exynos/clock-exynos5.c | 34
> > +++++++++++++++++++--------
> > arch/arm/plat-samsung/include/plat/clock.h | 2 +
> > 2 files changed, 26 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> > b/arch/arm/mach-exynos/clock-exynos5.c
> > index 774533c..205d19f 100644
> > --- a/arch/arm/mach-exynos/clock-exynos5.c
> > +++ b/arch/arm/mach-exynos/clock-exynos5.c
> > @@ -891,6 +891,13 @@ static struct clk exynos5_clk_mdma1 = {
>
> [.....]
>
> >
> > +struct clksrc_clk exynos5_clk_sclk_fimd = {
>
> Replace 'exynos5_clk_sclk_fimd' with 'exynos5_clk_sclk_fimd1'.
> This is because 'exynos5_clk_sclk_fimd0' can be added for other
> Exynos5 SoCs later.
>
Okay, will change it and post the next version.
> Best regards,
> Jingoo Han
>
> > + .clk = {
> > + .name = "sclk_fimd",
> > + .devname = "exynos5-fb.1",
> > + .enable = exynos5_clksrc_mask_disp1_0_ctrl,
> > + .ctrlbit = (1 << 0),
> > + },
> > + .sources = &exynos5_clkset_group,
> > + .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4
> > },
> > + .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4
> > },
> > +};
> > +
>
>
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