Shaik Ameer Basha wrote:
>
> Add required clock support for Gscaler for exynos5
>
Hi,
Cc'ed Sunyoung Kang who knows gscaler well in my team.
> Signed-off-by: Abhilash Kesavan <a.kesavan@xxxxxxxxxxx>
> Signed-off-by: Leela Krishna Amudala <l.krishna@xxxxxxxxxxx>
> Signed-off-by: Prathyush K <prathyush.k@xxxxxxxxxxx>
> Signed-off-by: Shaik Ameer Basha <shaik.ameer@xxxxxxxxxxx>
> ---
> arch/arm/mach-exynos/clock-exynos5.c | 79
> ++++++++++++++++++++++++++++++++++
> 1 files changed, 79 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-
> exynos/clock-exynos5.c
> index fefa336..c8293a3 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -741,6 +741,26 @@ static struct clk exynos5_init_clocks_off[] = {
> .enable = exynos5_clk_ip_peric_ctrl,
> .ctrlbit = (1 << 14),
> }, {
> + .name = "gscl",
> + .devname = "exynos-gsc.0",
> + .enable = exynos5_clk_ip_gscl_ctrl,
> + .ctrlbit = (1 << 0),
Sunyoung, I've seen (1 << 15) | (1 << 0) here instead, which one is right?
[snip]
I think, following part should be moved between
---
static struct clksrc_clk exynos5_clk_aclk_66 = {
[snip]
};
<<<HERE>>>
static struct clk exynos5_init_clocks_off[] = {
---
Please don't put your clock code without any checking the clock code.
> +/* For ACLK_300_gscl_mid */
> +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
> + .clk = {
> + .name = "mout_aclk_300_gscl_mid",
> + },
> + .sources = &exynos5_clkset_aclk,
> + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
> +};
> +
> +/* For ACLK_300_gscl */
> +struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
> + [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
> + [1] = &exynos5_clk_sclk_vpll.clk,
As I know, this is wrong. Its [1] should be
&exynos5_clk_mout_aclk_300_gscl_mid1.clk
> +};
> +
> +struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
> + .sources = exynos5_clkset_aclk_300_gscl_list,
> + .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
> +};
> +
> +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
> + .clk = {
> + .name = "mout_aclk_300_gscl",
> + },
> + .sources = &exynos5_clkset_aclk_300_gscl,
> + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_dout_aclk_300_gscl = {
> + .clk = {
> + .name = "dout_aclk_300_gscl",
> + .parent = &exynos5_clk_mout_aclk_300_gscl.clk,
> + },
> + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 },
> +};
> +
> +/* Possible clock sources for aclk_300_gscl_sub Mux */
> +static struct clk *clk_src_gscl_300_list[] = {
> + [0] = &clk_ext_xtal_mux,
> + [1] = &exynos5_clk_dout_aclk_300_gscl.clk,
> +};
> +
> +static struct clksrc_sources clk_src_gscl_300 = {
> + .sources = clk_src_gscl_300_list,
> + .nr_sources = ARRAY_SIZE(clk_src_gscl_300_list),
> +};
> +
> +static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
> + .clk = {
> + .name = "aclk_300_gscl",
> + },
> + .sources = &clk_src_gscl_300,
> + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
> +};
> +
[snip]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@xxxxxxxxxxx>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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