Hi Shaik,
Some nits:
Patch subject: s/EXYNOS5/EXYNOS
On 6 July 2012 18:15, Shaik Ameer Basha <shaik.ameer@xxxxxxxxxxx> wrote:
> Add required clock support for Gscaler for exynos5
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@xxxxxxxxxxx>
> Signed-off-by: Leela Krishna Amudala <l.krishna@xxxxxxxxxxx>
> Signed-off-by: Prathyush K <prathyush.k@xxxxxxxxxxx>
> Signed-off-by: Shaik Ameer Basha <shaik.ameer@xxxxxxxxxxx>
> ---
> arch/arm/mach-exynos/clock-exynos5.c | 79 ++++++++++++++++++++++++++++++++++
> 1 files changed, 79 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
> index fefa336..49f98cd 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -741,6 +741,26 @@ static struct clk exynos5_init_clocks_off[] = {
> .enable = exynos5_clk_ip_peric_ctrl,
> .ctrlbit = (1 << 14),
> }, {
> + .name = "gscl",
> + .devname = "exynos-gsc.0",
> + .enable = exynos5_clk_ip_gscl_ctrl,
> + .ctrlbit = (1 << 0),
> + }, {
> + .name = "gscl",
> + .devname = "exynos-gsc.1",
> + .enable = exynos5_clk_ip_gscl_ctrl,
> + .ctrlbit = (1 << 1),
> + }, {
> + .name = "gscl",
> + .devname = "exynos-gsc.2",
> + .enable = exynos5_clk_ip_gscl_ctrl,
> + .ctrlbit = (1 << 2),
> + }, {
> + .name = "gscl",
> + .devname = "exynos-gsc.3",
> + .enable = exynos5_clk_ip_gscl_ctrl,
> + .ctrlbit = (1 << 3),
> + }, {
> .name = SYSMMU_CLOCK_NAME,
> .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
> .enable = &exynos5_clk_ip_mfc_ctrl,
> @@ -1116,6 +1136,61 @@ static struct clksrc_clk exynos5_clksrcs[] = {
> },
> };
>
> +/* For ACLK_300_gscl_mid */
> +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
> + .clk = {
> + .name = "mout_aclk_300_gscl_mid",
> + },
> + .sources = &exynos5_clkset_aclk,
> + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
> +};
> +
> +/* For ACLK_300_gscl */
> +struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
> + [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
> + [1] = &exynos5_clk_sclk_vpll.clk,
> +};
> +
> +struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
> + .sources = exynos5_clkset_aclk_300_gscl_list,
> + .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
> +};
> +
> +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
> + .clk = {
> + .name = "mout_aclk_300_gscl",
> + },
> + .sources = &exynos5_clkset_aclk_300_gscl,
> + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_dout_aclk_300_gscl = {
> + .clk = {
> + .name = "dout_aclk_300_gscl",
> + .parent = &exynos5_clk_mout_aclk_300_gscl.clk,
> + },
> + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 },
> +};
> +
> +/* Possible clock sources for aclk_300_gscl_sub Mux */
> +static struct clk *clk_src_gscl_300_list[] = {
> + [0] = &clk_ext_xtal_mux,
> + [1] = &exynos5_clk_dout_aclk_300_gscl.clk,
> +};
> +
> +static struct clksrc_sources clk_src_gscl_300 = {
> + .sources = clk_src_gscl_300_list,
> + .nr_sources = ARRAY_SIZE(clk_src_gscl_300_list),
> +};
> +
> +static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
> + .clk = {
> + .name = "aclk_300_gscl",
> + },
> + .sources = &clk_src_gscl_300,
> + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
> +};
> +
> /* Clock initialization code */
> static struct clksrc_clk *exynos5_sysclks[] = {
> &exynos5_clk_mout_apll,
> @@ -1139,6 +1214,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
> &exynos5_clk_aclk_266,
> &exynos5_clk_aclk_200,
> &exynos5_clk_aclk_166,
> + &exynos5_clk_mout_aclk_300_gscl_mid,
> + &exynos5_clk_mout_aclk_300_gscl,
> + &exynos5_clk_dout_aclk_300_gscl,
> + &exynos5_clk_aclk_300_gscl,
> &exynos5_clk_aclk_66_pre,
> &exynos5_clk_aclk_66,
> &exynos5_clk_dout_mmc0,
Please maintain the alphabetic order.
> --
> 1.7.0.4
>
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--
With warm regards,
Sachin
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