Joonyoung Shim wrote:
> I don't understand this. Do you mean that BL1 codes do it?
> I also wonder how enable L2 cache at the exynos5.
Yes, the latency configuration of L2 cache is located on IROM or BL1 code.
It can remove the overhead about cache reset and cache flush.
And, Kernel enables L2 cache.
Thanks.
>
> > no longer need that in the kernel. It helps to reduce
> > booting time (no need cache disable and cache enable).
> >
> > Signed-off-by: Boojin Kim <boojin.kim@xxxxxxxxxxx>
> > Signed-off-by: Kukjin Kim <kgene.kim@xxxxxxxxxxx>
> > ---
> > arch/arm/mach-exynos/common.c | 25 -------------------------
> > 1 files changed, 0 insertions(+), 25 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> > index 742edd3..0ec1a91 100644
> > --- a/arch/arm/mach-exynos/common.c
> > +++ b/arch/arm/mach-exynos/common.c
> > @@ -712,31 +712,6 @@ static int __init exynos4_l2x0_cache_init(void)
> > early_initcall(exynos4_l2x0_cache_init);
> > #endif
> >
> > -static int __init exynos5_l2_cache_init(void)
> > -{
> > - unsigned int val;
> > -
> > - if (!soc_is_exynos5250())
> > - return 0;
> > -
> > - asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
> > - "bic %0, %0, #(1 << 2)\n" /* cache disable */
> > - "mcr p15, 0, %0, c1, c0, 0\n"
> > - "mrc p15, 1, %0, c9, c0, 2\n"
> > - : "=r"(val));
> > -
> > - val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
> > -
> > - asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
> > - asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
> > - "orr %0, %0, #(1 << 2)\n" /* cache enable */
> > - "mcr p15, 0, %0, c1, c0, 0\n"
> > - : : "r"(val));
> > -
> > - return 0;
> > -}
> > -early_initcall(exynos5_l2_cache_init);
> > -
> > static int __init exynos_init(void)
> > {
> > printk(KERN_INFO "EXYNOS: Initializing architecture\n");
> > --
> > 1.7.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>
>
> --
> - Joonyoung Shim
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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