On 24 May 2012 12:57, Kukjin Kim <kgene.kim@xxxxxxxxxxx> wrote: > Thomas Abraham wrote: >> >> The sclk_spi clock is derived currently from the first level divider >> (MMCx_RATIO) which is incorrect. The output of the first level clock >> is divided by a second level divider (MMCx_PRE_RATIO), the output of >> which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy >> issues for the sclk_spi clock. >> >> Signed-off-by: Thomas Abraham <thomas.abraham@xxxxxxxxxx> >> Acked-by: Jaswinder Singh <jaswinder.singh@xxxxxxxxxx> >> --- >> arch/arm/mach-exynos/clock-exynos4.c | 48 > ++++++++++++++++++++++++++++-- >> --- >> 1 files changed, 40 insertions(+), 8 deletions(-) >> >> diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach- >> exynos/clock-exynos4.c >> index 10a46a9..b5f0507 100644 >> --- a/arch/arm/mach-exynos/clock-exynos4.c >> +++ b/arch/arm/mach-exynos/clock-exynos4.c >> @@ -1242,40 +1242,70 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { >> .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, >> }; >> >> +static struct clksrc_clk exynos4_clk_mdout_spi0 = { > > In this case, it's expected that 'exynos4_clk_dout_spi0' will be used even > though this indicates the clock of mux_out and divider_out together. > >> + .clk = { >> + .name = "sclk_spi_mdout", > > So, this should be 'dout_spi0' This clock instance has both a mux and a divider. So I used mdout to mean that there is both a mux and a divider in this clock instance. If you insist on changing the name to dout_spi0, I will change it. Thanks, Thomas. > >> + .devname = "exynos4210-spi.0", > > [...] > > Thanks. > > Best regards, > Kgene. > -- > Kukjin Kim <kgene.kim@xxxxxxxxxxx>, Senior Engineer, > SW Solution Development Team, Samsung Electronics Co., Ltd. > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html