On Mon, Oct 10, 2011 at 02:02:09PM +0100, Marc Zyngier wrote:
> On 07/10/11 16:16, Will Deacon wrote:
> > On Fri, Oct 07, 2011 at 10:44:59AM +0100, Marc Zyngier wrote:
> >> +static void __cpuinit exynos4_secondary_init(unsigned int cpu)
> >> {
> >> void __iomem *dist_base = S5P_VA_GIC_DIST +
> >> - (gic_bank_offset * smp_processor_id());
> >> + (gic_bank_offset * cpu_logical_map(cpu));
> >
> > Again, I'm deeply suspicious of this code :) Is there not a common memory
> > alias for the distributor across all of the CPUs?
>
> Kukjin, could you please comment on the presence of a common memory
> region for the distributor? This seem quite odd...
It's not odd when you consider that there's per-CPU registers within the
GIC distributor as well (for the first 32 GIC IRQs) as the per-CPU GIC
CPU interfaces.
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