Kukjin Kim wrote: > > Grant Likely wrote: > > > > On Mon, Jul 4, 2011 at 12:55 AM, Grant Likely <grant.likely@xxxxxxxxxxxx> > wrote: > > > On Fri, Jul 01, 2011 at 11:43:08AM +0530, Jassi Brar wrote: > > >> On Fri, Jul 1, 2011 at 11:29 AM, padma venkat <padma.kvr@xxxxxxxxx> > wrote: > > >> > Hi Jassi, > > >> > > > >> > On Fri, Jul 1, 2011 at 11:22 AM, Jassi Brar > <jassisinghbrar@xxxxxxxxx> wrote: > > >> >> On Fri, Jul 1, 2011 at 11:16 AM, padma venkat <padma.kvr@xxxxxxxxx> > > wrote: > > >> >>> Hi Tony, > > >> >>> > > >> >>> On Thu, Jun 30, 2011 at 4:30 PM, Tony Nadackal <tonykn@xxxxxxxxx> > > wrote: > > >> >>>> Hi Padma, > > >> >>>> With regards to your patch, even though one can check the tx done > > status > > >> >>>> using the TX_DONE bit, the present macro itself would work > perfectly > > fine if > > >> >>>> the 'fifo_lvl_mask' is set properly. > > >> >>>> For example in 6450 channel 1, the fifo_lvl_mask should be 0x1ff > (for > > 9bits, > > >> >>>> 15:23), while even in your patch, it is wrongly set as 0x7f(only > 7bits). > > >> >>>> > > >> >>>> Thus, if this fifo_lvl_mask was defined correctly, the existing > macro > > would > > >> >>>> itself have worked. > > >> >>> Thanks for your comment. > > >> >>> I considered changing to the fifo_lvl_mask to 1ff as you mentioned. > > >> >>> But I think that the fifo_lvl_mask reflects the actual FIFO > capacity > > >> >>> in the SPI driver. > > >> >>> For the failing channels the FIFO trigger level is 64 bytes and so > i > > >> >>> retained that value. > > >> >>> In the driver it polls till the FIFO capacity level otherwise it > goes > > >> >>> for DMA.So if we keep > > >> >>> the FIFO level as 1ff when the actual capacity is 7f then it fails. > > >> >>> > > >> >>> Jassi what do you think about this? > > >> >>> > > >> >> > > >> >> 'fifo_lvl_mask' is h/w specific and can't be set for convenience. > > >> >> > > >> >> I don't have access to post-s3c64xx datasheets. > > >> >> Please check and reply if TX_DONE bit is at same offset for all > > >> >> channels of an SoC, because > > >> >> I suspect it's otherwise. > > >> >> > > >> > Yes. The TX_DONE bit is at the same offset for all the channels of an > SoC. > > >> > in S5P64X0,S5PV210 and S5PV310 it is at offset 25. > > >> > > > >> > > >> Then, Patches-1,2 > > >> > > >> Acked-by: Jassi Brar <jassisinghbrar@xxxxxxxxx> > > > > > > Are these bug fixes that should be in v3.0, or do I queue them up for > v3.1? > > > > Regardless, this one touches a lot of arch/arm files, so I'd rather > > see both patches go through the samsung tree: > > > > Acked-by: Grant Likely <grant.likely@xxxxxxxxxxxx> > > > > Thanks Grant, Jassi and all, > > I will apply these 1 and 2 in my -fix tree for 3.0 with your acks. > Oops, this needs previous 'cleanup spi platform specific code' so can't apply -fix tree now. Padmavathi, I will apply these 1 and 2 on -next for 3.1 after your updated 'cleanup spi' patches... If any problems, please let me know. Thanks. Best regards, Kgene. -- Kukjin Kim <kgene.kim@xxxxxxxxxxx>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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